Split Gate Memory Cell Height Reduction via Segmented Control Gate
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Solution Overview
Problem
As device critical dimensions shrink, it becomes challenging to match the height of split-gate memory cells with logic devices, particularly when the control gate extends up and over the floating gate, and there is a need to reduce memory cell height to accommodate multiple metal lines and tight design rules.
Innovation Solution
A method is developed to form a memory array with a thinner polysilicon floating gate and a thicker control gate oxide, allowing the control gate to wrap around the floating gate for high erase efficiency, while reducing the overall height of the memory cells to match the low profile of logic devices, using a process that includes specific layer formations and etching techniques to achieve improved word line-floating gate coupling and higher voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control gate extends up and over the floating gate to maintain wrap-around structure, then erase efficiency is improved, but the memory cell height increases making it difficult to match logic device height
Solution Approach 1:
The control gate is segmented into two distinct portions: a first control gate portion and a second control gate portion. This segmentation allows each portion to be independently formed with optimized thickness and positioning, enabling the wrap-around structure to achieve erase efficiency while controlling overall height through selective thinning of the first portion.
Solution Approach 2:
Different regions of the control gate are given different thickness characteristics. The first control gate portion is made thinner than the second control gate portion, creating local quality variations. This allows the wrap-around region to have sufficient thickness for erase efficiency while other regions are thinned to reduce overall cell height and match logic device profiles.
2Productivity
If device critical dimensions are shrunk to match logic device scaling, then integration density is improved, but the height mismatch between memory cells and logic devices becomes more difficult to resolve
Solution Approach 1:
The control gate thickness is made dynamic rather than uniform throughout. By selectively thinning the first control gate portion while maintaining a thicker second portion, the structure adapts to different functional requirements: the thinner first portion reduces overall height for scaling compatibility, while the thicker second portion maintains erase efficiency for the wrap-around region.
3Adaptability or versatility
If multiple metal lines are added to accommodate tight design rules, then functionality is improved, but the required vertical space increases making height reduction more challenging
Solution Approach 1:
Segmenting the control gate into two portions with different thicknesses enables the structure to accommodate multiple metal lines by reducing the overall height profile. The thinner first control gate portion creates vertical space for additional metal interconnect layers while the thicker second portion maintains the necessary electrical performance for erase operations.
Data Source
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AI summary
A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.