Split Gate Memory Cell With Logic Gate On Same Substrate
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Solution Overview
Problem
Integrating split-gate memory cells with other field-effect devices on the same semiconductor substrate is challenging due to differing fabrication parameters, which affects cost, performance, and manufacturability.
Innovation Solution
A method of forming a semiconductor device with a split gate memory cell and logic gate on the same substrate, where the memory cell and logic gate have different gate lengths, allowing for distinct fabrication processes in different regions, enabling efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If split-gate memory cells and non-memory devices are integrated on the same substrate, then device functionality and integration density are improved, but fabrication process complexity increases due to differing fabrication parameters
Solution Approach 1:
The substrate is divided into distinct regions: a first region for split-gate memory cells and a second region for non-memory devices. This spatial segmentation allows each region to be optimized for its specific device type with appropriate fabrication parameters, while maintaining overall integration on the same substrate.
Solution Approach 2:
Different fabrication parameters are applied to different regions of the substrate. The first region receives fabrication conditions optimized for memory cells, while the second region receives conditions optimized for non-memory devices, allowing each area to have locally optimized quality without compromising the other.
2Reliability
If multiple device types require different fabrication parameters, then device performance is optimized, but manufacturing efficiency and cost decrease
Solution Approach 1:
By segmenting the substrate into dedicated regions for different device types, the patent enables simultaneous optimization of fabrication parameters for each device type while maintaining streamlined manufacturing. Each region can be processed with its optimal parameters without requiring separate production lines.
Solution Approach 2:
The patent merges the fabrication processes for memory cells and non-memory devices into a single integrated manufacturing flow on one substrate. Despite different local parameters, the overall process is combined rather than separated, improving manufacturing efficiency and reducing costs.
Data Source
AI summary
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.