Split-Gate Memory Cell Gate Electrode Thickness Optimization
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Solution Overview
Problem
The miniaturization of gate electrodes in semiconductor devices leads to issues such as ion penetration, deterioration of high withstand voltage MISFET characteristics, and junction leakage due to insufficient sidewall spacer width, which affects the reliability and performance of nonvolatile memory cells.
Innovation Solution
The implementation of a split-gate type memory cell structure with a thicker control gate and a larger aspect ratio for the memory gate, along with a halo region, to prevent ion penetration and ensure adequate sidewall spacer width, thereby maintaining the integrity of the gate insulating film and improving hot carrier resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode is miniaturized to improve device integration, then device density increases, but ion penetration occurs and high withstand voltage MISFET characteristics deteriorate
Solution Approach 1:
The patent applies different gate electrode thicknesses to different device regions: a first thickness for low withstand voltage MISFETs and a second, greater thickness for high withstand voltage MISFETs. This local differentiation allows miniaturization in low-voltage devices while maintaining reliability in high-voltage devices, resolving the contradiction between integration and characteristic preservation.
Solution Approach 2:
The patent changes the physical parameter of gate electrode thickness to resolve the contradiction. By adjusting the thickness parameter locally across different device types, the patent enables miniaturization where appropriate while maintaining sufficient thickness to prevent ion penetration and preserve high withstand voltage characteristics where needed.
2Length of moving object
If the gate electrode thickness is reduced to improve miniaturization, then device density increases, but ion penetration and junction leakage occur
Solution Approach 1:
The patent implements local quality by assigning different gate electrode thicknesses to different functional regions: thinner gates for low-voltage devices where miniaturization is beneficial, and thicker gates for high-voltage devices where ion penetration resistance is critical. This spatial differentiation eliminates ion penetration and junction leakage in high-voltage devices while achieving miniaturization goals in low-voltage devices.
3Productivity
If the gate electrode is miniaturized to increase device density, then integration improves, but sidewall spacer width becomes insufficient
Solution Approach 1:
The patent applies local quality by differentiating gate electrode dimensions across device types. The thicker gate electrodes in high-voltage devices provide adequate sidewall spacer width to prevent junction leakage, while thinner gates in low-voltage devices achieve higher density. This localized approach resolves the contradiction between device density and sidewall spacer adequacy.
Data Source
AI summary
In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.