Split Gate Memory Cell With Vertical Selection And Horizontal Control Gates
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Solution Overview
Problem
Conventional split gate memory cells occupy more semiconductor surface area and lack flexibility in controlling electrical characteristics due to their vertical arrangement and shared control and selection gates, limiting their programming efficiency and footprint compared to single-control-gate flash memory cells.
Innovation Solution
A memory cell structure with a vertical selection gate and a horizontal control gate, where the floating gate extends over the selection gate with a non-zero overlap, and a thicker dielectric layer near the substrate surface, allowing for a protuberance that enhances programming and erasing capabilities through distinct voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical arrangement of selection gate and control gate is used, then the semiconductor surface area is reduced, but the flexibility in controlling electrical characteristics is lost
Solution Approach 1:
The gate structure is segmented into a vertical selection gate and a horizontal control gate that are physically separated and independently controllable. This segmentation allows the memory cell to maintain a compact footprint while enabling independent voltage application to each gate, thus providing flexibility in controlling electrical characteristics for different operations (programming, erasing, reading).
Solution Approach 2:
The invention transitions from a conventional planar arrangement to a three-dimensional configuration where the selection gate extends vertically and the control gate extends horizontally. This dimensional change reduces the surface footprint while creating distinct spatial zones that can be independently biased, thereby maintaining control flexibility.
2Ease of manufacture
If a shared conductive layer forms both control gate and selection gate, then manufacturing is simplified, but independent voltage control is lost
Solution Approach 1:
The previously shared conductive layer is segmented into two separate conductive layers: one forming the vertical selection gate and another forming the horizontal control gate. This segmentation enables independent voltage control while maintaining manufacturing feasibility through sequential deposition and patterning processes.
Solution Approach 2:
The solution moves from a two-dimensional planar gate structure to a three-dimensional configuration with vertical and horizontal components formed by separate conductive layers. This spatial separation enables independent electrical control while the manufacturing process remains compatible with standard semiconductor fabrication techniques.
3Manufacturing precision
If the floating gate is completely separated from the selection gate, then manufacturing precision is improved, but programming efficiency decreases
Solution Approach 1:
The floating gate structure exhibits non-uniform characteristics: it has a protuberance that extends beneath the substrate surface to overlap with the vertical selection gate in the programming region, while maintaining separation in other areas. This local variation enables efficient hot-electron injection during programming while maintaining overall structural integrity and manufacturability.
Solution Approach 2:
The floating gate contains a protuberance that nests within the spatial envelope defined by the selection gate structure. This nested configuration allows the floating gate to extend into the region occupied by the selection gate, creating an overlap zone that enhances programming efficiency without requiring complete gate separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the semiconductor surface area occupied, improves programming efficiency by allowing separate control of gate oxides, and simplifies the memory array architecture with fewer interconnection lines, while maintaining the advantages of vertical selection transistor sections.
Implementation Method 1
The selection transistor section has a conductive channel in which a current appears, which comprises high kinetic energy electrons, referred to as 'hot electrons'. When this current reaches the conductive channel of the floating-gate transistor section, an injection zone appears where the high energy electrons are injected into the floating gate under the effect of a transverse electric field created by the voltage applied to the control gate.
Implementation Method 2
an injection zone appears where the high energy electrons are injected into the floating gate under the effect of a transverse electric field created by the voltage applied to the control gate
Data Source
AI summary
The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.