Split Gate Memory Cells Thinner Tunnel Oxide
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Solution Overview
Problem
The existing method for forming split-gate non-volatile memory cells requires a thick oxide layer for the control gate while also needing to be thin enough for efficient tunneling, leading to suboptimal erase performance and increased manufacturing complexity due to the need for separate tunnel and word line oxides.
Innovation Solution
A method where a first oxide layer is formed with a sharp edge, followed by a non-uniform etching process to thin the oxide layer specifically at the edge, and then a second deposition to maintain the thickness variation, allowing for a thinner tunnel oxide while using the same oxide layer for both tunnel and word line oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick oxide layer is used for the control gate to ensure operational performance, then the control gate performance is improved, but the tunneling efficiency deteriorates due to increased thickness
Solution Approach 1:
The patent applies local quality by creating a non-uniform oxide layer where the thickness varies spatially. The oxide layer is thinner at the tunneling region (between floating gate and control gate) to enable efficient electron tunneling, while being thicker at the control gate region to maintain operational performance. This is achieved through selective thinning processes that modify the oxide layer thickness at specific locations rather than using a uniform thickness throughout.
2Reliability
If separate tunnel oxide and word line oxide layers are formed to optimize both tunneling and control gate performance, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by using a single oxide layer that serves multiple functions simultaneously. The same oxide layer acts as both the tunnel oxide (enabling electron tunneling between floating and control gates) and the word line oxide (insulating the control gate). By making the oxide layer non-uniform in thickness, the patent enables this single layer to fulfill both roles optimally, eliminating the need for separate tunnel oxide and word line oxide formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances erase efficiency and endurance by allowing easier electron tunneling through the reduced thickness oxide layer, while maintaining operational performance and simplifying manufacturing by using a single oxide layer for multiple functions.
Implementation Method 1
performing a non-uniform etching process to thin the oxide layer specifically at the edge
Implementation Method 2
performing a second deposition to maintain the thickness variation
Implementation Method 3
electrons tunnel through this dielectric material during the erase operation
Data Source
AI summary
A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.