Split Gate Memory Cell Array Scalability via Converging Control Gates
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Solution Overview
Problem
In split gate memory cells, achieving high access speed for the select gate while minimizing space requirements is challenging, especially as feature sizes reduce, and existing layouts often need significant changes to accommodate faster switching without increasing size.
Innovation Solution
Converging adjacent control gates near select gate contacts allows for closer spacing of select gates and reduces the need for additional space, enabling low impedance signal propagation without requiring tabs or additional spacing, thus maintaining performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the select gate is made with larger spacing and additional space is allocated, then low impedance and fast switching speed are achieved, but the array size increases and scalability is compromised
Solution Approach 1:
Adjacent control gates are merged or converged into a common control gate structure that serves multiple memory cells. This consolidation eliminates the need for separate control gate spacing for each cell, freeing up space that can be reallocated to reduce select gate spacing and improve switching speed without increasing overall array size
Solution Approach 2:
The control gates are arranged in a converging three-dimensional configuration rather than parallel planar arrangement. This dimensional change allows control gates to share common contact regions and reduces the lateral space required, enabling tighter select gate spacing while maintaining proper control gate functionality
2Speed
If feature sizes are reduced to improve speed, then switching speed increases, but manufacturing precision requirements increase and layout changes are needed
Solution Approach 1:
The common control gate structure serves multiple memory cells simultaneously, providing a universal solution that works across different feature sizes. This multi-functional design maintains proper electrical characteristics and spacing relationships regardless of scaling, reducing the need for layout redesign when transitioning to smaller feature sizes
Solution Approach 2:
The converging control gate configuration changes the geometric parameters of the gate structure, creating self-similar scaling relationships that maintain electrical performance across different feature sizes. This parameter optimization allows speed improvement through scaling without proportionally increasing manufacturing precision requirements
Data Source
AI summary
A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.