Split-Gate Memory Cell Programming Current Peak Elimination

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Solution Overview

Problem

Existing split-gate memory cell programming techniques experience a current peak at the start of the programming pulse, leading to inefficiencies and the need for over-dimensioning charge pump circuits when programming multiple cells simultaneously, which can result in insufficient threshold voltage and reduced programming efficiency.

Innovation Solution

Applying a variable voltage to the gate of the selection transistor during programming, transitioning between a first and a second value greater than the first, to modulate the programming current without affecting the vertical electric field, thereby eliminating the current peak and maintaining programming efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a constant voltage is applied to the gate of the selection transistor during programming, then the programming process is simple to control, but a current peak appears at the start of the programming pulse which forces the charge pump circuit to be over-dimensioned

Engineering Contradiction:
Improvecontrol simplicityVSAvoidcharge pump circuit dimensioning
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent applies a dynamic voltage to the gate of the selection transistor that evolves over time during the programming pulse. The voltage starts at a first value and transitions to a second value, which modulates the programming current to eliminate the initial current peak while maintaining effective hot carrier injection throughout the programming duration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter applied to the selection transistor gate from a constant value to a time-varying value. This parameter change allows optimization of the programming current profile, eliminating the harmful initial peak while maintaining sufficient current for effective programming throughout the pulse duration.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the voltage applied to the gate of the selection transistor is lowered to attenuate the current peak, then the charge pump circuit can be smaller, but the programming efficiency drops and the threshold voltage of the floating gate transistor becomes insufficient

Engineering Contradiction:
Improvecharge pump circuit dimensioningVSAvoidprogramming efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent uses a dynamic voltage profile that increases during the programming pulse, allowing the system to start with lower voltage (reducing current peak) and progressively increase to higher voltage (maintaining programming efficiency). This temporal evolution of the voltage parameter resolves the contradiction between reducing current peak and maintaining programming effectiveness.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies a preliminary lower voltage at the start of the programming pulse to prevent the harmful current peak, then transitions to a higher voltage to ensure sufficient programming efficiency. This staged approach to voltage application allows the charge pump circuit to be smaller while maintaining effective programming.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a high voltage is applied to the control gate of the state transistor for effective programming, then the hot electron injection performance is improved, but a current peak appears at the start of the programming pulse

Engineering Contradiction:
Improvehot electron injection performanceVSAvoidcurrent peak
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different voltage characteristics to different parts of the programming process: a lower initial voltage to the selection transistor gate to prevent current peak, and a high voltage to the control gate of the state transistor to maintain effective hot electron injection. This localized differentiation of voltage application resolves the contradiction between preventing current peak and maintaining injection performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the voltage applied to the selection transistor gate during the programming pulse, allowing the system to maintain high voltage at the control gate for effective programming while modulating the selection transistor gate voltage to eliminate the harmful current peak at the start of the pulse.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for efficient programming of split-gate memory cells by eliminating the current peak at the start of the pulse, ensuring sufficient threshold voltage differentiation between programmed and erased states, and reducing the risk of read disturbances.

Implementation Method 1

The selection transistor has a conductive channel in which a current is formed including high kinetic energy electrons, called 'hot electrons'. When this current reaches the conductive channel of the state transistor, an injection area is formed where the high-energy electrons are injected into the floating gate

Methodology Applied
Scientific EffectHot electron injection: Electron Beam

Implementation Method 2

an injection area is formed where the high-energy electrons are injected into the floating gate of this transistor under the effect of a vertical electric field created by the voltage applied to the control gate of the state transistor

Methodology Applied
Scientific EffectElectric field: Electric Field

Data Source

PatentUS10796763B2Method for programming a split-gate memory cell and corresponding memory device
Publication Date: 2020.10.06 STMICROELECTRONICS (ROUSSET) SAS
  • US10796763B2 patent drawing
  • US10796763B2 patent drawing
  • US10796763B2 patent drawing

AI summary

A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.