3D Split-Gate Memory Array Layout for Higher Cell Density
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Solution Overview
Problem
Current split-gate flash memory structures face challenges in optimizing memory cell integration density and capacity due to the need for further reduction in memory cell area.
Innovation Solution
A split-gate memory array design with a 3D structure, where memory cell groups are distributed along two directions, and selection and storage transistors share gates and sources, reducing external holes and horizontal area, and a row operation mode for simultaneous data erasing and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional flash memory structures are used, then manufacturing and programming are relatively simple, but memory cell area is large and integration density is low
Solution Approach 1:
The patent merges two selection transistors into a single shared gate structure, and combines storage and selection functions within the same physical footprint. This merging reduces the number of discrete transistor components from four to three per memory cell, directly decreasing memory cell area while maintaining the necessary selection and storage functionality through the shared gate mechanism
Solution Approach 2:
The patent introduces a vertical dimension by stacking the split-gate structure, where selection transistors are positioned above storage transistors in a three-dimensional arrangement. This vertical integration allows multiple memory cells to be packed more densely in the horizontal plane, reducing overall memory cell footprint and improving integration density without significantly increasing lateral complexity
2Quantity of substance
If memory cell area is reduced to increase integration density, then capacity enhancement is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The shared gate structure serves multiple functions simultaneously: it acts as the gate for both selection transistors and provides a common control interface. This multi-functionality reduces the number of separate gate structures needed, simplifying the manufacturing process and reducing alignment precision requirements despite the reduced memory cell area
Solution Approach 2:
The memory array is segmented into multiple memory cell groups arranged in a grid pattern, with each group containing shared selection transistors. This segmentation allows for modular manufacturing where alignment requirements are localized to smaller groups rather than requiring precision across the entire array, making high-density integration more manufacturable
Data Source
AI summary
A split-gate memory array and a method for operating same. The array comprises: a memory array including a plurality of memory cell groups, each memory cell group comprising a first memory cell and a second memory cell, wherein the first memory cell comprises a first storage transistor and a first selection transistor which are formed by means of a split-gate structure, and the second memory cell comprises a second storage transistors and a second selection transistors which are formed by means of a split-gate structure; gate electrodes of the first selection transistors in the same row are connected, gate electrodes of the second selection transistors in the same row are connected, the selection transistors and the storage transistors use a split-gate structure, and the gate electrodes of adjacent selection transistors are connected together to reduce the number of external connection holes, thereby reducing the area of the memory cells.