Split-Gate Memory Integration via Dielectric Isolation
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Solution Overview
Problem
Integrating split-gate cells with other field-effect devices on the same substrate is challenging due to differing fabrication parameters, requiring improved methods for performance, cost, and manufacturability.
Innovation Solution
A semiconductor device with a memory gate and select gate separated by a dielectric structure, including a silicon nitride or silicon oxynitride layer, is fabricated using specific etching and deposition techniques to form memory and logic gates, allowing for efficient integration with other field-effect devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If split-gate cells are integrated with other field-effect devices on the same substrate, then device functionality and efficiency are improved, but fabrication complexity increases due to differing fabrication parameters
Solution Approach 1:
The patent applies universality by developing a common fabrication process that can manufacture both split-gate memory cells and other field-effect devices (such as logic transistors and capacitors) on the same substrate. The process uses standardized layers including a substrate, insulating layer, electrode layers, and dielectric layers that serve multiple device types, allowing diverse functionality to be integrated without requiring separate fabrication lines.
Solution Approach 2:
The patent employs parameter changes by adjusting the electrical characteristics of the substrate and insulating layer based on the specific device type being fabricated. Different voltage thresholds, doping concentrations, and layer thicknesses are applied to different regions of the substrate to accommodate both low-voltage logic devices and high-voltage memory devices within the same fabrication process.
2Speed
If high drain and gate voltages are used for programming, then programming speed is improved, but current consumption increases which is undesirable in low power applications
Solution Approach 1:
The patent applies dynamics by implementing a split-gate configuration where the select gate voltage can be dynamically adjusted during programming operations. The select gate voltage is modulated to control carrier injection efficiency, allowing the device to achieve fast programming when needed while reducing current consumption during normal operation. The gate voltages are dynamically changed based on the programming state requirements.
Solution Approach 2:
The patent uses parameter changes by varying the select gate voltage and memory gate voltage independently during different programming phases. The select gate voltage is adjusted to optimize the tunneling barrier height, while the memory gate voltage is modulated to control charge injection into the floating gate. This dynamic parameter adjustment enables fast programming speed while maintaining low average current consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of split-gate cells with other field-effect devices, improving performance, reducing power consumption, and enhancing manufacturability while maintaining low current and low power consumption during programming.
Implementation Method 1
A semiconductor device with a memory gate and select gate separated by a dielectric structure, including a silicon nitride or silicon oxynitride layer, is fabricated using specific etching and deposition techniques
Implementation Method 2
During the programming of the split-gate cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection
Implementation Method 3
A Flash memory cell is commonly programmed using hot carrier injection to inject charge carriers either onto a floating gate or into charge trapping sites in a dielectric layer underlying a control gate of a FET
Data Source
AI summary
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.