Split Gate Memory Cell Erase Gate Delay Programming
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Solution Overview
Problem
Existing non-volatile memory cells with floating gates face rapid degradation of insulating layers and interfaces due to high initial voltage applied during programming, leading to reduced program/erase endurance.
Innovation Solution
A method where a third positive voltage is applied to the erase gate with a delay after the start of other voltage pulses, reducing the maximum potential on the floating gate and minimizing stress on insulating layers, thereby improving program/erase endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high initial voltage is applied to the erase gate during programming, then hot electron injection efficiency is improved, but insulating layer degradation accelerates
Solution Approach 1:
The erase gate voltage is applied with a delay after the channel formation voltage, so that the channel is already formed before the high voltage is applied to the erase gate. This preliminary channel formation allows efficient hot electron injection while reducing the stress on the insulating layer during the voltage transition phase.
Solution Approach 2:
The programming operation uses a multi-stage voltage application sequence where voltages are applied in distinct time periods: first forming the channel, then applying the erase gate voltage with a delay. This periodic/staged approach optimizes both injection efficiency and device reliability.
2Productivity
If the erase gate voltage is applied simultaneously with other voltage pulses, then programming efficiency is maximized, but peak floating gate potential causes rapid degradation
Solution Approach 1:
The channel formation voltage is applied first to prepare the conduction path, and only after this preliminary action is complete (with a specified delay) is the erase gate voltage applied. This sequencing prevents simultaneous voltage application that would create excessive peak potentials on the floating gate.
Solution Approach 2:
The delay period between channel formation and erase gate voltage application acts as a cushioning interval, allowing the device to transition smoothly into the high-voltage state without experiencing abrupt stress that would degrade the insulating layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The delayed application of the erase gate voltage reduces peak floating gate potential, minimizing degradation of insulating layers and interfaces, resulting in enhanced endurance of the memory cell.
Implementation Method 1
electrons are injected to the floating gate 24 through hot-electron injection with the portion of the channel 18 under the floating gate 24 in inversion
Implementation Method 2
Electrons are transferred from the floating gate 24 to the erase gate 28 by Fowler-Nordheim tunneling through the insulating layer between the floating gate 24 and the erase gate 28
Data Source
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AI summary
During the programming of a non-volatile memory cell, a voltage pulse is applied to an erase gate of the cell a delay time after voltage pulses are applied to the other elements of the cell. The erase gate voltage pulse ends at substantialy the same time as the other voltage pulses end.