Split Gate Memory Erase Gate Polysilicon Tunnel Oxide Integrity
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Solution Overview
Problem
The use of high K metal material for erase gates in split gate non-volatile memory devices introduces high-density traps on the tunnel oxide, leading to poor performance and retention failure, while replacing it with polysilicon can damage the underlying tunnel oxide.
Innovation Solution
Forming logic gates using high K metal material but initially using polysilicon for the erase gate, which protects the tunnel oxide from HKMG-related processing steps, and avoiding the formation of the HKMG layer in the erase gate area to prevent trap introduction and oxide damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high K metal material is used for erase gate, then logic device performance is improved, but tunnel oxide integrity deteriorates due to high-density traps
Solution Approach 1:
The substrate is divided into memory cell area and logic device area, with the HKMG layer selectively formed only in the logic device area. This segmentation allows high K metal gates to be used for logic devices while preventing trap introduction in the memory cell area where tunnel oxide integrity must be maintained.
Solution Approach 2:
Different gate structures are used in different areas: polysilicon gates are used in the memory cell area to protect tunnel oxide, while high K metal gates are used in the logic device area to improve performance. This local differentiation resolves the contradiction by optimizing each area for its specific function.
2Object-affected harmful factors
If polysilicon is used for erase gate to protect tunnel oxide, then tunnel oxide integrity is maintained, but device performance deteriorates compared to high K metal gates
Solution Approach 1:
The gate structure is segmented by area: polysilicon erase gates protect the tunnel oxide in memory cells, while high K metal gates provide superior performance in logic devices. This segmentation allows each material to be used where it provides the greatest benefit without compromising the other requirements.
Solution Approach 2:
The isolation region acts as an intermediary barrier that prevents the HKMG layer from extending into the memory cell area. This intermediary structure enables the coexistence of polysilicon gates (for oxide protection) and high K metal gates (for performance) on the same substrate.
3Ease of manufacture
If HKMG layer is formed across the entire substrate, then manufacturing simplicity is improved, but memory cell performance deteriorates due to trap introduction
Solution Approach 1:
The HKMG layer formation process is segmented into two stages: first forming the layer across the entire substrate for manufacturing simplicity, then selectively removing it from the memory cell area to prevent trap introduction. This segmented approach maintains ease of manufacture while protecting memory cell performance.
Solution Approach 2:
The HKMG layer is extracted from the memory cell area after initial formation. This extraction removes the harmful element (high K metal material that introduces traps) from the memory cell region while preserving the benefits of unified initial formation for manufacturing simplicity.
Data Source
Figure 1
Figure 2A~2F
Figure 3A~3B
AI summary
A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.