Split Gate Nonvolatile Memory Cell Erasure Process
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Solution Overview
Problem
The silicon nanocrystals in the select gate set of split gate nonvolatile memory cells are difficult to erase and affect the threshold voltage of memory cells, posing a challenge in the formation of electronic devices.
Innovation Solution
A process is developed where a semiconductor layer is formed over the substrate, spaced apart from the control gate electrode, and a select gate electrode is formed over the semiconductor layer, with an insulating spacer and thinner gate dielectric layers used to facilitate the formation of nonvolatile memory cells, ensuring that no silicon nanocrystals lie between the control and select gate electrodes, thereby improving erasure efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nanocrystals are formed between the control gate electrode and select gate electrode in split gate nonvolatile memory cells, then charge storage capability is improved, but erasure difficulty increases and threshold voltage control deteriorates
Solution Approach 1:
The patent extracts the problematic select gate set of silicon nanocrystals by repositioning the charge storage stack so that it lies only between the control gate electrode and substrate, not between the control and select gate electrodes. This removes the source of erasure difficulties while preserving charge storage functionality in the substrate-set nanocrystals.
Solution Approach 2:
The patent changes the spatial arrangement of the charge storage stack by introducing a stepped substrate structure with different elevations. The charge storage stack is positioned on a first region of the substrate at a lower elevation, while the select gate electrode is formed on a second region at a higher elevation, effectively separating the charge storage location from the select gate electrode path.
2Reliability
If silicon nancrystals are formed between control gate electrode and select gate electrode, then nonvolatile memory functionality is achieved, but threshold voltage stability deteriorates
Solution Approach 1:
The patent removes silicon nanocrystals from the region between the control gate electrode and select gate electrode, eliminating their unwanted influence on threshold voltage. The charge storage function is retained solely in the substrate-set nanocrystals located between the control gate electrode and substrate, providing stable threshold voltage control.
3Speed
If select gate dielectric layer is removed from exposed regions to create substrate step, then ballistic injection capability is improved, but silicon nanocrystals remain in problematic positions
Solution Approach 1:
The patent segments the substrate into different elevation regions: a first region at lower elevation where the charge storage stack with silicon nanocrystals is formed, and a second region at higher elevation where the select gate electrode is formed. This segmentation ensures that silicon nanocrystals are confined to the lower region, preventing them from being in problematic positions between the gates while maintaining the substrate step for ballistic injection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the erasability of silicon nanocrystals and reduces their impact on threshold voltage, improving the programming and erasing capabilities of nonvolatile memory cells without requiring additional masking layers, thus integrating seamlessly into existing manufacturing processes.
Implementation Method 1
selectively growing a semiconductor layer from an exposed portion of the substrate
Implementation Method 2
thermally oxidizing the substrate to form the control gate dielectric layer
Data Source
AI summary
An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.