Split Gate Nonvolatile Memory Device with Acute-Angled Floating Gate
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Solution Overview
Problem
In split gate-type nonvolatile semiconductor memory devices, the inability to form a thin gate insulating film under the control gate during data erasing leads to reduced read speed due to the need for a high potential applied to the control gate, which compromises the reliability and efficiency of data erasure.
Innovation Solution
The formation of an acute-angled portion on the floating gate facing the erase gate, achieved by incurving both side surfaces of the floating gate, allows for improved electric field concentration during data erasure without exposing the semiconductor substrate and thus preventing the occurrence of a 'divot', enabling a thinner gate insulating film and enhanced erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high potential is applied to the control gate to achieve FN tunneling during data erasing, then data erasing is achieved, but the gate insulating film cannot be made thin, reducing read speed
Solution Approach 1:
The gate structure is segmented into a control gate and a separate erase gate. The erase gate is specifically designed to apply high potential for FN tunneling during data erasing, while the control gate maintains a thinner gate insulating film for optimized read speed. This segmentation allows each gate to be optimized for its specific function without compromise.
2Speed
If the gate insulating film is made thin to improve read speed, then read speed increases, but high potential application during erasing becomes unreliable
Solution Approach 1:
The gate structure is segmented into a control gate and a separate erase gate. The erase gate is specifically designed to apply high potential for FN tunneling during data erasing, while the control gate maintains a thinner gate insulating film for optimized read speed. This segmentation allows each gate to be optimized for its specific function without compromise.
3Productivity
If an acute-angled portion is formed on the floating gate to concentrate electric field, then erase efficiency improves, but divot formation may occur compromising substrate integrity
Solution Approach 1:
The floating gate is designed with acute-angled portions only at specific locations where it faces the erase gate, rather than having sharp edges throughout. This localized geometry concentrates the electric field precisely where needed for efficient electron extraction to the erase gate, while avoiding divot formation in other regions that would compromise substrate integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves erase efficiency and speed while maintaining device reliability by concentrating the electric field at acute-angled portions of the floating gate, allowing for effective electron extraction to the erase gate without compromising the integrity of the semiconductor substrate.
Implementation Method 1
the data erasing is achieved by an FN (Fowler-Nordheim) tunneling method. More specifically, a high potential is applied to the control gate, and electrons in the floating gate are extracted to the control gate through a tunnel insulating film due to the FN tunneling
Implementation Method 2
This approach improves erase efficiency and speed while maintaining device reliability by concentrating the electric field at acute-angled portions of the floating gate, allowing for effective electron extraction to the erase gate
Data Source
AI summary
A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation structure having a first projecting portion; and a second device isolation structure having a second projecting portion. The first and second projecting portions have a first sloping surface and a second sloping surface, respectively. The first sloping surface and the second sloping surface face each other, and an interval between the first and second sloping surfaces becomes larger away from the semiconductor substrate. The floating gate is sandwiched between the first and second projecting portions and at least has a portion located on the semiconductor substrate side of the first and second sloping surfaces.