Split Gate Memory Cells With High K Metal Gate Integration
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Solution Overview
Problem
The existing methods for forming split gate non-volatile memory devices on the same chip as logic and high voltage devices often result in degradation of the memory cell structure during processing.
Innovation Solution
A method is developed to protect the memory cell structure by forming isolation regions and subsequent layers using specific etching and deposition techniques, including the use of high K metal gate layers and insulation materials, to prevent degradation during the formation of logic devices on the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high K metal gate layers are formed during logic device processing, then logic device performance is improved, but memory cell structure degradation occurs
Solution Approach 1:
The chip is divided into distinct memory cell regions and logic device regions, with isolation regions separating them. This segmentation allows different processing conditions to be applied to each region - the logic regions receive high K metal gate processing while the memory regions are protected from degradation
Solution Approach 2:
Isolation regions act as intermediary structures between memory cell regions and logic device regions. These isolation regions buffer and protect the memory cell structures from the harmful effects of high K metal gate processing while still allowing the logic devices to benefit from the processing
2Reliability
If memory cell structure is protected during processing, then structure integrity is maintained, but processing complexity increases
Solution Approach 1:
The isolation regions serve multiple functions simultaneously: they electrically isolate memory cells from logic devices, physically protect memory structures during processing, and define region boundaries. By merging these functions into a single structural element, the overall processing complexity is reduced despite the protective function
Data Source
Figure 1
Figure 2A~2F
Figure 3A
AI summary
A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.