Split-Gate Non-Volatile Memory Integration with Logic Regions
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Solution Overview
Problem
Integrating split-gate non-volatile memory cells with other field-effect devices on the same semiconductor substrate is challenging due to differing electrical requirements, such as varying gate stack thickness and implantation energy needs for high-speed and high-voltage operations, which complicates fabrication and performance.
Innovation Solution
A method of manufacturing a semiconductor device with distinct regions for memory and logic gates, where the gate dielectric and conductor layers are formed and etched to create a select gate, memory gate, and logic gates with varying thicknesses, allowing for separate processing and integration of devices with different electrical requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single gate stack thickness is used for all devices on the substrate, then fabrication is simplified, but high-speed transistors cannot achieve optimal performance due to insufficient gate control
Solution Approach 1:
The patent implements different gate stack thicknesses in different regions of the same substrate. Memory cells receive a first gate stack thickness optimized for their electrical requirements, while high-speed transistors receive a second, thinner gate stack thickness to improve gate control and switching speed. This spatial variation in gate stack quality resolves the contradiction by allowing each device type to have locally optimized characteristics without complicating the overall fabrication process.
2Reliability
If high implantation energy is used for all devices, then high-voltage transistors achieve proper junction depth, but low-voltage transistors suffer from excessive implant penetration and damaged characteristics
Solution Approach 1:
The patent divides the substrate into distinct processing regions that receive different ion implantation energies. High-voltage transistor regions undergo implantation at higher energies to achieve the required junction depth for voltage handling, while low-voltage transistor regions receive lower energy implantation to preserve their electrical characteristics. This segmentation of the implantation process allows each device type to receive tailored processing without compromising overall manufacturing compatibility.
3Reliability
If region isolation structures are added to enable different processing parameters for different devices, then device performance is optimized, but fabrication complexity and cost increase
Solution Approach 1:
The patent introduces isolation structures that create vertical and lateral separation between different device regions. These isolation elements enable independent processing of memory cells and high-speed transistors by providing physical boundaries that allow different implantation energies, gate stack thicknesses, and other processing parameters to be applied to adjacent regions without cross-interference. The added dimensional separation resolves the contradiction by organizing complexity in a structured manner that enables performance optimization while maintaining reasonable fabrication control.
Data Source
AI summary
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.