Split-Gate Memory Charge Storage Isolation

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Solution Overview

Problem

In split-gate memory arrays, charge stored in nanocrystals migrates over time, reducing the memory array's performance due to lack of effective charge storage isolation, as traditional methods use continuous charge storage layers that allow charge diffusion between neighboring nanocrystals.

Innovation Solution

The implementation of isolated charge storage regions using split-gate memory arrays with multiple control and select gate electrodes, where each electrode is electrically isolated from others via layers, and source/drain regions are isolated from both control and select gates, preventing charge migration through the use of specific deposition and etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If continuous charge storage layers are used, then manufacturing is simpler, but charge migration occurs between neighboring nanocrystals

Engineering Contradiction:
Improvecharge storage layer fabricationVSAvoidcharge storage isolation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The continuous charge storage layer is divided into isolated nanocrystal regions separated by insulating materials. This segmentation prevents charge migration between neighboring storage regions while maintaining manufacturing feasibility through controlled deposition and etching processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulating materials are introduced as intermediary layers between adjacent charge storage regions. These intermediary insulating layers act as barriers that prevent charge diffusion while allowing the overall structure to be fabricated using standard semiconductor manufacturing techniques.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If charge storage isolation is implemented, then charge migration is prevented, but device complexity increases

Engineering Contradiction:
Improvecharge storage isolationVSAvoidmemory array structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory array structure is segmented into discrete bit cells with isolated charge storage regions. Each bit cell contains nanocrystals confined within insulating barriers, creating a modular structure that prevents charge migration while maintaining organizational simplicity at the array level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Insulating materials are selectively placed in specific locations between charge storage regions rather than uniformly throughout the structure. This local quality approach provides necessary isolation where needed while minimizing overall structural complexity and maintaining ease of fabrication.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces or eliminates charge migration, allowing the memory array to maintain sufficient charge storage capacity over time, enabling better performance and scalability of memory arrays.

Implementation Method 1

electrically isolated from one another by bit line isolation regions

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

charge stored in nanocrystals migrates over time

Methodology Applied
Scientific EffectCharge storage: Capacitance

Data Source

PatentUS9136360B1Methods and structures for charge storage isolation in split-gate memory arrays
Publication Date: 2015.09.15 NXP USA INC
  • US9136360B1 patent drawing
  • US9136360B1 patent drawing
  • US9136360B1 patent drawing

AI summary

Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.