Self-Aligned Split-Gate Memory Structure for Low-Power Operation
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Solution Overview
Problem
Conventional non-volatile memory cells require high currents for operation, making them unsuitable for low-power devices, and existing EEPROM structures face challenges in reducing cell size due to alignment tolerance requirements, limiting high cell density.
Innovation Solution
A self-aligned split-gate memory structure is developed, comprising a first conductive line, conductive blocks, dielectric spacers, and a second conductive line, allowing for charge storage and functioning as select and floating gates, with doping regions and the second conductive line acting as bit and word lines, enabling efficient programming, reading, and erasure without the need for alignment tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional non-volatile memory cells are used, then data storage capability is achieved, but high current consumption occurs making them unsuitable for low-power devices
Solution Approach 1:
The gate structure is segmented into a control gate and a select gate, allowing independent control of programming and read/erase operations. This segmentation enables the memory cell to operate with lower currents by activating only the necessary gate during each operation phase, thereby reducing overall power consumption while maintaining reliability.
Solution Approach 2:
The patent introduces a vertical stack configuration with control gate and select gate positioned at different spatial locations and operating at different voltage potentials. This dimensional separation allows the memory cell to achieve low-power operation by confining high-voltage programming operations to the control gate while read operations use lower voltages on the select gate, effectively managing power consumption across different operational states.
2Manufacturing precision
If floating gate is made larger than select gate for alignment tolerance, then alignment robustness is improved, but cell size increases limiting high cell density
Solution Approach 1:
The memory structure employs self-aligned fabrication processes where the select gate and control gate are automatically positioned relative to each other through sequential deposition and patterning steps. The dielectric spacer serves as a self-defined alignment reference, eliminating the need for additional alignment margins and enabling minimum cell size without compromising manufacturing precision.
Solution Approach 2:
The patent adopts an asymmetric gate configuration where the control gate and select gate have different dimensions and positions optimized for their specific functions. The control gate extends further in the channel direction to provide adequate control, while the select gate is positioned to enable proper selectivity. This asymmetric design achieves both alignment robustness and compact cell size by optimizing each gate's geometry for its specific operational role rather than requiring symmetric dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for significantly increased cell density and reduced power consumption, achieving competitive small memory cell sizes and improved operational efficiency by eliminating the need for alignment tolerance, thus enhancing low-power device capabilities.
Implementation Method 1
the stack of the conductive block, the first dielectric layer, and the second conductive line form a typical floating gate structure, i.e., the conductive block can store charges
Implementation Method 2
The first conductive line and conductive blocks function as a select gate and floating gates, respectively, whereas the doping regions and the second conductive line function as bit lines and a word line
Implementation Method 3
two doping regions, in a semiconductor substrate
Data Source
AI summary
An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions. While reading the programmed status of one of the conductive blocks, a bias voltage is applied to the doping region next to the conductive block to be read, a bias voltage is applied to the second conductive line, and a bias voltage is applied to the first conductive line next to the conductive block to be read, so as to turn on the select gate and form an inversion layer underneath the select gate; and the doping region, the channel under the conductive block and the inversion layer under the select gate form a reading path during the reading operation.