Split Gate Memory Cell Low Voltage Operation
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Solution Overview
Problem
Prior memory cells in user-programmable integrated circuits require higher voltages for programming and erasing, which necessitate the fabrication of other transistor devices to withstand these voltages, leading to inefficiencies and potential damage during normal circuit operation.
Innovation Solution
A split-gate push-leak memory cell design featuring a compact two-transistor cell with a select gate over a thin oxide portion and a control gate over a nano-crystal/SONOS stack, utilizing a p-channel pull-up transistor and a low-voltage n-channel switch transistor to reduce standby leakage and operate at lower voltages, allowing for low-voltage bit-line operation and fast programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If higher voltages are used for programming and erasing memory cells, then programming and erasing operations can be performed, but other transistor devices must be fabricated to withstand these higher voltages, increasing device complexity and potential damage risk
Solution Approach 1:
The memory cell is divided into two distinct voltage domains: a high-voltage region for programming/erasing operations and a low-voltage region for normal circuit operation. The select gate transistor is isolated from the main memory transistor, allowing it to operate at low voltages while the memory transistor experiences high voltages only during programming/erasing. This segmentation resolves the contradiction by preventing high-voltage stress on all devices.
Solution Approach 2:
The select gate transistor acts as an intermediary device that controls the connection between the low-voltage bit line and the high-voltage memory transistor. During normal operation, it provides low-voltage switching. During programming/erasing, it isolates the low-voltage circuitry from the high-voltage stress, enabling the memory transistor to withstand programming voltages without compromising other devices.
2Ease of manufacture
If higher voltages are used for programming and erasing, then memory operations can be performed, but the risk of damage to transistor devices during normal circuit operation increases
Solution Approach 1:
The circuit is segmented into voltage-isolated regions using the select gate transistor as a barrier. This ensures that high-voltage programming/erasing operations are confined to the memory transistor only, protecting other low-voltage devices from damage while maintaining programming functionality.
Solution Approach 2:
The select gate transistor is positioned to provide voltage isolation before high-voltage stress can affect other devices. During normal operation, it maintains low-voltage conditions; during programming/erasing, it prevents high-voltage propagation to vulnerable circuit elements, cushioning them against damage in advance.
3Ease of manufacture
If conventional memory cell designs are used, then programming and erasing can be achieved, but standby leakage current is high and cell size is large
Solution Approach 1:
The memory cell is segmented into functionally independent parts: the select gate transistor for low-voltage switching and the memory transistor for high-voltage storage. This segmentation enables the use of smaller, lower-leakage transistors in the low-voltage region while maintaining high-voltage programming capability in the isolated memory region, reducing overall standby leakage.
Solution Approach 2:
The invention changes the voltage operating parameters by introducing a dual-voltage architecture. The select gate operates at low voltage (reducing its leakage), while the memory transistor operates at high voltage only during programming/erasing. This parameter separation reduces standby leakage compared to conventional single-voltage designs.
4Ease of manufacture
If conventional memory cell designs are used, then programming can be performed, but programming speed is slow and current consumption is high
Solution Approach 1:
By segmenting the memory cell into select gate and memory transistor components with independent voltage domains, the invention enables fast hot-carrier injection programming. The low-voltage select gate can be turned on quickly to enable the high-voltage memory transistor without requiring high currents during normal operation, thereby increasing programming speed while controlling current consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced standby leakage, low on-state switch impedance, compact cell size, and low-current, fast hot-carrier-injection programming while minimizing the need for high-voltage fabrication techniques, ensuring reliable operation and reducing the risk of damage during programming and erasing.
Implementation Method 1
a control gate over a nano-crystal/SONOS stack, and a gap between the two gates
Implementation Method 2
low-current, fast hot-carrier-injection programming
Data Source
AI summary
A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.