Self-Aligned Split-Gate Memory Cell Array With Metal Gates
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Solution Overview
Problem
Existing methods for forming memory cell arrays face challenges in efficiently creating self-aligned split-gate memory cells with metal gates and integrating both low and high voltage logic devices on the same wafer die, particularly in terms of precise gate formation and alignment.
Innovation Solution
A method involving a semiconductor substrate with sequential deposition and etching of polysilicon layers, insulation layers, and implantation processes to form self-aligned floating, control, and select gates, with metal gates replacing polysilicon gates, allowing for precise undercut and vertical sidewall formation to enhance memory cell structure and reduce photolithography masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional photolithography masking steps are used to form memory cell gates, then gate formation is achieved, but the process complexity and number of steps increase
Solution Approach 1:
The patent employs self-aligned processes where previously formed structures serve as alignment references for subsequent gate formation. The select gate and control gate are formed using self-aligned techniques that eliminate the need for separate photolithography masking steps, as each gate structure automatically aligns to the other through the self-aligned process
Solution Approach 2:
The patent performs preliminary formation of the select gate and control gate structures before final gate definition. By pre-forming these gates with self-aligned techniques and using them as reference structures, subsequent processing steps can proceed without additional masking, as the gates are already in their correct relative positions
2Productivity
If memory cell arrays and logic devices are formed separately, then each device type can be optimized, but wafer space utilization and manufacturing efficiency decrease
Solution Approach 1:
The patent employs a universal process flow that can form both memory cell arrays and logic devices on the same wafer using the same fabrication steps. The self-aligned gate formation process is applicable to both device types, allowing simultaneous optimization of wafer space utilization and manufacturing precision through a unified manufacturing approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of fully self-aligned memory cells and logic devices with improved gate structures, reducing the number of masking steps and ensuring precise alignment, thus enhancing the efficiency and reliability of memory cell arrays.
Implementation Method 1
forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type
Implementation Method 2
forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer
Implementation Method 3
depositing a first polysilicon layer over and insulated from the substrate
Data Source
AI summary
A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.