Split-Gate Memory Device Area Reduction via Mirrored Gate Structures
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Solution Overview
Problem
The miniaturization of split-gate memory devices is hindered by the need for additional wiring space and area in the memory cell region for control gates, which also requires a peripheral control gate decoder circuit, making it unfavorable for higher integration.
Innovation Solution
A split-gate memory device with mirrored first and second gate structures and a source region, where control gates of the first and second gate structures are electrically connected through electrical connections, eliminating the need for separate wiring space and peripheral control gate decoder circuits, and a method for forming such a device that includes etching and spacer formation to expose these connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If control gates are wired out separately in the memory cell region, then control functionality is achieved, but wiring space and area increase
Solution Approach 1:
The patent merges the control gates of the first and second gate structures by electrically connecting them together, allowing them to be controlled by a single control gate line rather than requiring separate wiring for each control gate. This combining approach reduces the wiring space and overall area of the memory cell region while maintaining the necessary control functionality.
2Measurement precision
If separate peripheral control gate decoder circuits are added, then control precision is improved, but device complexity increases
Solution Approach 1:
The patent eliminates the need for separate peripheral control gate decoder circuits by merging the control functions. The mirrored gate structures share common control gates and electrical connections, which simplifies the overall circuit design and reduces device complexity while maintaining adequate control precision through the shared control mechanism.
Data Source
AI summary
A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.