Split Gate Memory Device Using Negative Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Prior art non-volatile memory cells do not utilize negative voltages during read, program, and erase operations, limiting their efficiency and scalability.
Innovation Solution
Applying a negative voltage to the word line, coupling gate, and/or floating gate of non-volatile memory cells during these operations, utilizing a negative charge pump circuit and control circuit to generate and control the necessary voltages, which includes a decoder circuit and high voltage regulation to manage the voltage levels for accurate programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If negative voltage is applied to word line, coupling gate, and floating gate during read, program, and erase operations, then programming accuracy and reading accuracy are improved with reduced leakage and power consumption, but device complexity increases due to the need for negative charge pump circuit and voltage control circuitry
Solution Approach 1:
A negative charge pump circuit is introduced as an intermediary component to generate the required negative voltages for word line, coupling gate, and floating gate during program and erase operations. This mediator enables accurate voltage control without directly complicating the memory cell structure itself, as the charge pump can be implemented as a separate support circuit.
Solution Approach 2:
The patent applies negative voltage parameters to the word line, coupling gate, and floating gate during program and erase operations, fundamentally changing the voltage regime from conventional positive/zero voltages. This parameter change enables improved programming accuracy and reduced leakage by creating appropriate electric field conditions for charge injection and removal.
2Reliability
If negative voltage is applied to unselected memory cells during program operations, then cell disturb is reduced, but manufacturing complexity increases due to additional voltage regulation and control circuits
Solution Approach 1:
Negative voltage is applied selectively to unselected word lines during program operations, creating different voltage conditions for selected versus unselected cells. This local differentiation protects unselected cells from disturb while allowing programming of selected cells, implementing quality differentiation across spatially distinct regions.
Solution Approach 2:
Negative voltage is pre-applied to unselected word lines before the program operation commences on selected cells. This preliminary action establishes protective voltage conditions in advance, preventing potential charge injection or interference from occurring in the first place.
3Manufacturing precision
If negative voltage is used during erase operations, then erase completeness is improved, but power consumption increases due to the negative charge pump circuit
Solution Approach 1:
Negative voltage parameters are applied to the word line and coupling gate during erase operations to create strong electric fields that facilitate complete charge removal from the floating gate. This parameter change enables more thorough erasure by overcoming charge retention effects that limit conventional positive-voltage erase methods.
Data Source
AI summary
A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.