Split Gate Memory Cell With Overlapping Erase Gate
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Solution Overview
Problem
Existing split gate flash memory cell designs face challenges in achieving the performance advantages of 4-gate devices while maintaining smaller device geometries and reducing manufacturing masking steps.
Innovation Solution
A three-gate memory cell configuration with a conductive floating gate, an erase gate that wraps over the floating gate, and a word line gate laterally adjacent to the floating gate, eliminating the need for a coupling gate and allowing for capacitive coupling during programming, along with the use of metal word line gates surrounded by high K dielectric for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 4-gate configuration is used to achieve improved erase capability and performance, then erase capability is improved, but device geometry becomes larger and manufacturing complexity increases
Solution Approach 1:
The patent combines the erase gate and coupling gate into a single integrated structure. The erase gate includes a first portion laterally adjacent to the floating gate and a second portion extending over the floating gate, eliminating the need for a separate coupling gate while maintaining the necessary capacitive coupling functionality for programming and providing effective erase capability
Solution Approach 2:
The integrated erase gate structure serves multiple functions: it provides erase capability through the first portion laterally adjacent to the floating gate, and it provides capacitive coupling for programming through the second portion extending over the floating gate. This multi-functional design replaces what would traditionally require separate gates
2Reliability
If a 4-gate configuration is used to achieve improved erase capability, then erase capability is improved, but the number of masking steps during manufacturing increases
Solution Approach 1:
The patent merges the erase gate and coupling gate into a single integrated structure formed in one continuous deposition and patterning sequence. This is achieved by forming the erase gate with a first portion laterally adjacent to the floating gate and a second portion extending over the floating gate, which can be accomplished in a single manufacturing step rather than requiring separate masking steps for separate gates
3Area of stationary object
If device geometry is reduced to achieve smaller cell size, then device area is reduced, but achieving adequate erase capability becomes more difficult
Solution Approach 1:
The patent extends the erase gate vertically in the third dimension with a second portion that extends up and over the floating gate. This vertical extension provides additional erase capability and enhanced voltage coupling without increasing the lateral footprint of the device, allowing effective erase functionality in reduced geometries
Solution Approach 2:
The erase gate's second portion is positioned to extend over the floating gate, creating a nested configuration where the erase gate structure encompasses part of the floating gate vertically. This nested arrangement maximizes the erase field interaction while minimizing lateral space requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced cell height, improved erase capability, and simplified manufacturing processes with fewer masking steps, maintaining high cell current and speed while allowing for self-aligned formation of the floating gate and source line.
Implementation Method 1
The opposing region has such a shape that multiple electric field concentrating portions are formed when the erase voltage is applied to the erase gate electrode
Implementation Method 2
a floating gate electrode provided over the semiconductor layer via a first insulation film
Data Source
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AI summary
A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.