Split Gate Memory Cell With Re-oxidized Sidewall Layers
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Solution Overview
Problem
The fabrication of non-volatile memory (NVM) devices faces reliability and yield issues due to silicon substrate gauging and floating gate gauging during processing, affecting the performance of memory cells.
Innovation Solution
A method for forming memory cells with a split gate structure, where re-oxidized layers are formed on the sidewalls of the control gate, and a common source/drain region is shared between adjacent memory cells, with an erase gate disposed over the common source/drain region, enhancing the reliability and performance of the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processing is used, then manufacturing simplicity is maintained, but floating gate gauging and silicon substrate gauging occur causing reliability issues
Solution Approach 1:
A sacrificial oxide layer is formed on the silicon substrate before forming the floating gate. This preliminary oxidation creates a buffer layer that prevents direct contact between the floating gate and substrate, eliminating silicon substrate gauging. The sacrificial oxide is later removed to complete the floating gate formation without affecting substrate thickness.
Solution Approach 2:
The sacrificial oxide layer acts as an intermediary material between the silicon substrate and the floating gate electrode. This intermediate layer prevents the harmful interaction that causes substrate gauging, allowing the floating gate to be formed without directly etching or thinning the substrate.
2Speed
If floating gate thickness is reduced to improve device performance, then speed and efficiency improve, but manufacturing precision becomes difficult to control
Solution Approach 1:
The floating gate electrode is formed using a self-aligned process where the gate pattern defines its own boundaries. The etch process automatically stops at the desired thickness by using the gate pattern itself as the etch stop reference, eliminating the need for complex thickness monitoring and control mechanisms.
Solution Approach 2:
Traditional mechanical thickness control methods (physical measurement and adjustment) are replaced with a chemical etch-stop mechanism. The etch process uses material layer boundaries as natural stopping points, substituting mechanical precision requirements with chemical process control that is inherently more precise and repeatable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of NVM devices by preventing floating gate and silicon substrate gauging, allowing for better control of the floating gate electrode thickness and reducing manufacturing costs, while being compatible with existing logic processing techniques.
Implementation Method 1
Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalk of the control gate
Data Source
AI summary
Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.