Split-Gate Memory Cell Scaling via Segmented Gates

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Solution Overview

Problem

Conventional embedded flash memory devices face scalability issues due to limited cell size and increased channel region area, which prevents them from being competitive in modern flash memory applications, especially as they require larger source junctions to prevent punch-through and improve read current degradation.

Innovation Solution

A split-gate silicon-rich-nitride based non-volatile memory device, such as the SG-SOROS cell, is developed with a smaller cell size of less than 180 nm, utilizing source side hot carrier injection for fast write speeds and channel direct tunneling for erase operations, allowing for lower operating voltages and smaller cell dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If source junction is graded to prevent punch-through and improve read current degradation, then device reliability is improved, but channel region area increases and cell scalability deteriorates

Engineering Contradiction:

Improvedevice reliabilityVSAvoidchannel region area

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The gate structure is segmented into two separate gates: a control gate for programming/erasing operations and a select gate for channel control. This segmentation allows the select gate to provide punch-through prevention and read current stability without requiring a large graded source junction, thereby reducing the channel region area while maintaining device reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The select gate acts as an intermediary element between the source and the charge storage layer. It provides the necessary electrical control to prevent punch-through and stabilize read current without requiring the source junction to be heavily graded, thus reducing the area occupied by the channel region while maintaining reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If conventional split gate floating gate device with source side junction Fowler-Nordheim tunnel erase is used, then page erase functionality is provided, but cell size is large and scalability is limited

Engineering Contradiction:

Improvepage erase functionalityVSAvoidcell size

Core Design Contradiction:

Adaptability or versatilityVSArea of moving object

Solution Approach 1:

The conventional source side junction Fowler-Nordheim tunnel erase mechanism is replaced with a new mechanism where the select gate controls channel direct tunneling for erase operations. This substitution eliminates the need for large source junctions and enables smaller cell sizes while maintaining page erase functionality

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The erase mechanism parameters are changed from relying on source junction grading and Fowler-Nordheim tunneling to using channel direct tunneling controlled by the select gate. This parameter change enables effective page erase functionality with significantly reduced cell size and improved scalability

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The SG-SOROS memory device achieves faster access times, lower program and erase voltages, and compatibility with existing CMOS processes, reducing wafer and test costs while maintaining reliability, thus overcoming scalability limitations and enhancing performance.

Implementation Method 1

channel direct tunneling

Methodology Applied

Scientific EffectDirect tunneling:

Implementation Method 2

negative charges are injected from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer

Methodology Applied

Scientific EffectCharge injection and storage:

Implementation Method 3

positive charges are directly tunneled from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the positive charges in the charge storage layer

Methodology Applied

Scientific EffectCharge injection and storage:

Implementation Method 4

source side hot carrier injection (i.e., hot electron injection), which allows for fast write speed

Methodology Applied

Scientific EffectHot carrier injection:

Data Source

PatentUS8125020B2Non-volatile memory devices with charge storage regions

Publication Date: 2012.02.28 PROMOS TECH INC

AI summary

A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.