Self-Aligned Split-Gate Memory Cell Array with Metal Gates
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Solution Overview
Problem
Existing methods for forming split-gate memory cells and integrating low and high voltage logic devices on the same wafer die face challenges in efficient space utilization and alignment, particularly in forming self-aligned structures with precise gate configurations.
Innovation Solution
A process is developed to form self-aligned split-gate memory cells with metal gates, involving a series of etching and deposition steps to create trenches, insulation layers, and metal gate formation, allowing for precise alignment and integration of memory cells and logic devices on the same wafer die, with the memory cells sharing common source and erase gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography masking steps are used to form memory cells and logic devices, then alignment precision can be achieved, but the number of processing steps increases and productivity decreases
Solution Approach 1:
The patent implements self-aligned fabrication where the memory cell structures automatically define the positions of logic device gates without requiring additional photolithography masking steps. The trench formations and gate material depositions are performed in a self-aligned manner, eliminating the need for separate alignment operations and reducing processing steps while maintaining precision.
Solution Approach 2:
The patent combines the formation of memory cell structures and logic device gates into a unified self-aligned process. The same trench formation and gate material deposition steps serve both memory cell and logic device fabrication, merging previously separate processing sequences into a single integrated flow that improves productivity without sacrificing alignment precision.
2Device complexity
If memory cells are formed with separate gate structures, then gate control is simplified, but space utilization efficiency decreases
Solution Approach 1:
The patent merges the control gate and erase gate structures into a unified gate stack configuration for memory cells. By forming both gates within the same trench structure and using shared gate materials, the design achieves compact space utilization while maintaining the functional complexity needed for split-gate memory operation.
Solution Approach 2:
The patent implements a nested gate structure where the control gate and erase gate are positioned in overlapping or adjacent vertical and horizontal configurations within the same memory cell footprint. This nesting arrangement allows both gates to occupy shared space efficiently, reducing the overall area required per memory cell while preserving individual gate control capabilities.
3Adaptability or versatility
If logic devices and memory cells are integrated on the same wafer die, then device versatility increases, but manufacturing complexity increases
Solution Approach 1:
The patent creates a universal fabrication process that can form both memory cell structures and logic device gates using the same trench formation, insulation deposition, and gate material deposition steps. This multi-functional approach allows a single manufacturing sequence to produce different device types, increasing versatility while avoiding the need for separate specialized processing lines.
Solution Approach 2:
The patent applies local quality by allowing different regions of the wafer to be selectively processed after the common self-aligned steps. While the base process is universal, local variations in trench patterns, gate material compositions, or subsequent processing can be applied to specific areas to create different device characteristics, enabling device integration without uniformly increasing manufacturing complexity across the entire wafer.
Data Source
Figure 1A~1B
Figure 2A~3B
Figure 4A~4B
AI summary
A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.