Split Gate Memory Cell Density via Self-Aligned Contact Etch Stops
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high memory array density and fast operation due to the limitations in the spacing and alignment of split gate memory cells, leading to increased distance for carriers to travel and reduced reliability.
Innovation Solution
The use of self-aligned contact etch stops in the fabrication process allows for closer placement of split gate memory cells, reducing the width of drain contacts and improving alignment, enabling faster operation and higher density by employing a hard mask to form contact etch stops during the selective etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used without self-aligned contact etch stops, then the fabrication process is simpler, but the spacing between split gate memory cells must be larger, reducing memory array density
Solution Approach 1:
The patent applies preliminary action by forming contact etch stops during the gate patterning process before the contact formation step. The hard mask layer is patterned to create contact etch stops that define the precise location where contacts will later be formed, ensuring accurate alignment without requiring additional alignment steps. This preliminary definition of contact locations enables closer spacing of memory cells while maintaining fabrication simplicity.
Solution Approach 2:
The contact etch stops serve a dual function: they act as both the pattern definition for contacts and as etch stop layers during subsequent etching processes. The same hard mask structure that defines contact locations also provides the etch stop function, eliminating the need for separate alignment markers or additional mask layers. This self-service approach maintains process simplicity while achieving high precision alignment.
2Quantity of substance
If split gate memory cells are placed closer together to increase density, then memory array density improves, but the distance carriers must travel increases, reducing operation speed
Solution Approach 1:
The patent resolves the spacing contradiction by transitioning to a vertical stacking architecture. Instead of placing memory cells side-by-side in a planar arrangement, the invention stacks multiple memory cells vertically along the channel direction. Each memory cell consists of a stack including the substrate, tunnel dielectric, floating gate, blocking dielectric, and control gate arranged in vertical layers. This vertical dimension enables high cell density without increasing lateral carrier transport distance, maintaining fast operation speeds while achieving high memory array density.
3Reliability
If larger spacing is used between memory cells for conventional alignment, then alignment reliability is maintained, but the memory device area increases, reducing overall density
Solution Approach 1:
The patent merges multiple functions into the contact etch stop structure. The hard mask pattern serves simultaneously as the contact location definition, the etch stop layer for subsequent contact hole etching, and the alignment reference for contact formation. This merging of functions eliminates the need for separate alignment markers or additional spacing, enabling precise contact alignment with minimal cell spacing and maximizing memory device density while maintaining alignment reliability.
Data Source
AI summary
A memory device and method of making the same are disclosed. The memory device includes a first split gate memory cell including a first memory stack located over a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split gate memory cell also includes a first select gate located adjacent to the first floating gate and the first control gate and a contact etch stop located over a portion of a top surface of the first select gate. The contact etch stop enables a narrowing of the drain contact via during an etch process. By narrowing the drain contact via, the density of split gate memory cells may be increased.