Split-Gate Non-Volatile Memory Sharp Tip Edge Fabrication
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Solution Overview
Problem
Existing split-gate non-volatile memories face issues with data retention due to leakage current caused by the thin tunneling dielectric layer, which is prone to Trap Assisted Tunneling (TAT) effects, leading to poor retention of stored charges.
Innovation Solution
A fabrication method for split-gate non-volatile memory that involves forming a floating gate with a sharp tip edge, allowing for an increased thickness of the tunneling dielectric layer between the floating and erasing gates, thereby reducing leakage current and enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the tunneling dielectric layer is reduced to improve erasing efficiency, then the tunneling efficiency between floating gate and erasing gate is improved, but leakage current increases due to Trap Assisted Tunneling effect
Solution Approach 1:
The patent applies local quality by creating a sharp tip edge structure at the top portion of the floating gate, where the width gradually decreases from bottom to top. This localized geometric modification concentrates the electric field at the sharp tip, enhancing Fowler-Nordheim tunneling efficiency without requiring a thin dielectric layer across the entire structure. The tunneling dielectric layer can be thicker in non-critical areas while maintaining effective tunneling at the sharp tip region.
Solution Approach 2:
The patent changes the geometric parameters of the floating gate by forming a sharp tip edge with gradually decreasing width from bottom to top. This parameter change transforms the electric field distribution, creating a concentrated field at the tip that enables efficient tunneling through a thicker dielectric layer, thereby resolving the contradiction between tunneling efficiency and leakage current.
2Reliability
If the thickness of the tunneling dielectric layer is increased to prevent leakage current, then data retention is improved, but tunneling efficiency for erasing deteriorates
Solution Approach 1:
The sharp tip edge structure creates a localized region of high electric field concentration, enabling efficient Fowler-Nordheim tunneling even through a thicker dielectric layer. This local field enhancement allows the use of thicker dielectric material (improving reliability) while maintaining tunneling performance through the concentrated field at the tip.
Solution Approach 2:
The sharp tip edge represents an extreme form of curvature where the radius of curvature approaches zero. This extreme curvature concentrates the electric field lines at the tip, creating a localized high-field region that enables tunneling through thicker dielectric material without sacrificing erasing speed.
3Ease of manufacture
If a conventional floating gate structure is used, then manufacturing is simpler, but leakage current occurs due to thin tunneling dielectric layer requirements
Solution Approach 1:
The invention maintains relative manufacturing simplicity while improving reliability by introducing a sharp tip edge structure. This can be achieved through standard semiconductor fabrication techniques such as anisotropic etching or selective removal of gate material. The local geometric modification enables thicker dielectric layers without requiring complete redesign of the manufacturing process.
Solution Approach 2:
The patent transitions from a conventional planar floating gate to a three-dimensional structure with a sharp tip edge. This dimensional change allows the gate to extend vertically with a tapered profile, creating the sharp tip that concentrates the electric field and enables thicker dielectric layers while maintaining tunneling efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases the Fowler-Nordheim tunneling effect and prevents leakage current, resulting in improved data retention and performance of the split-gate non-volatile memory.
Implementation Method 1
the FN tunneling effect between the floating gate and the erasing gate can be obviously increased
Implementation Method 2
reducing the thickness of the tunneling dielectric layer has the risk of causing leakage current, especially after programming/erasing endurance cycles due to Trap Assisted Tunneling (TAT) effect
Data Source
AI summary
The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.