Split-Gate Memory Cells With TiN Layer For Overlap Tolerance
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Solution Overview
Problem
Existing split-gate non-volatile memory cells face challenges with alignment issues during manufacturing, leading to excessive or insufficient overlap between the control and select gates, resulting in reduced yields and performance due to high resistance or poor isolation, exacerbated by scaling.
Innovation Solution
The use of a conductive layer with lower resistivity, such as titanium nitride, between the select and control gates allows for greater tolerance of overlap variations, achieved through a method involving the formation of sidewalls and dielectric layers using a reduced number of masking steps, enabling improved alignment and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a three mask lithography process is used to form control gate and select gate, then the gates can be formed with proper structure, but alignment errors cause excessive or insufficient overlap between gates leading to high resistance or poor isolation
Solution Approach 1:
A mandrel structure is introduced as an intermediary element during the formation of the control gate. The mandrel serves as a temporary placeholder that defines the precise position where the control gate will be formed, ensuring proper alignment with the select gate. After the control gate is formed, the mandrel is removed. This intermediary structure eliminates the need for complex multi-mask lithography alignment while maintaining precise gate overlap control.
2Ease of manufacture
If polysilicon layers are used for control gate and select gate, then the gates can be formed with standard materials, but misalignment results in too much or too little overlap causing high resistance or poor isolation
Solution Approach 1:
The mandrel structure is formed in advance before the control gate material is deposited. This preliminary action establishes the precise spatial relationship between the select gate and the future control gate position. By preparing this alignment reference structure beforehand, the subsequent control gate formation can proceed with standard lithography processes without requiring high-precision multi-mask alignment, thus maintaining ease of manufacture while achieving precise gate overlap.
3Area of moving object
If scaling is performed to reduce device size, then device density increases, but alignment errors have greater impact causing reduced yields and performance
Solution Approach 1:
The mandrel structure acts as a scaling-independent alignment reference. Whether the device is scaled to 10nm or 100nm, the mandrel provides a fixed geometric reference that defines the control gate position relative to the select gate. This eliminates the cumulative alignment errors that typically worsen with scaling, as each gate formation step references the mandrel rather than requiring precise alignment between multiple lithography masks.
Data Source
AI summary
Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.