Split Gate Memory Device U-Shaped Insulation Integration
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Solution Overview
Problem
The integration of nonvolatile memory cells and logic-based semiconductor devices on the same semiconductor substrate is challenging due to the height difference in gate stacks, making it difficult to efficiently manufacture split-gate memory devices like MONOS devices within existing process flows for high-performance transistor devices.
Innovation Solution
The development of a split-gate memory device with a conductive selection gate electrode and memory gate electrode, where insulating materials are strategically positioned between and around the gate electrodes to form a unique U-shaped configuration, allowing for efficient integration with existing transistor device manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional flash memory cells with separate control gate and floating gate are used, then nonvolatile memory functionality is achieved, but the gate stack height becomes much taller than logic transistor gates, making integration challenging
Solution Approach 1:
The gate structure is segmented into two separate gate electrodes: a control gate electrode and a memory gate electrode. This segmentation allows each gate to be independently positioned and sized, enabling the memory gate to be aligned with logic transistor gates while the control gate extends above to provide control functionality, thus resolving the height mismatch issue
Solution Approach 2:
The invention transitions from a vertical stacking approach to a lateral arrangement where the control gate and memory gate are positioned side-by-side in the planar dimension. The control gate electrode extends laterally beyond the memory gate electrode, allowing the memory gate to maintain the same height as logic transistors while the control gate provides overhead control functionality
2Length of stationary object
If split gate MONOS device structure is implemented, then gate stack height is reduced for better integration, but manufacturing efficiency and compatibility with existing process flows deteriorate
Solution Approach 1:
The method forms the control gate electrode and memory gate electrode in a predetermined sequence using standard semiconductor processing steps. The control gate is formed first, followed by the memory gate, with each step using conventional deposition, etching, and doping techniques that are already integrated into existing CMOS fabrication lines
Solution Approach 2:
The split gate structure uses universal semiconductor manufacturing processes that can fabricate both the memory device and logic transistors using the same equipment and material layers. The control gate and memory gate share common process steps such as gate oxide formation, polysilicon deposition, and source/drain doping, enabling seamless integration into existing process flows
Data Source
AI summary
One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.