Split Gate Semiconductor Memory Device Uniformity
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Solution Overview
Problem
Non-volatile semiconductor memory devices, such as flash memory devices, face issues with parasitic capacitance and uniformity in cell characteristics due to overlay variations in photolithography during the formation of split gates, leading to reliability concerns.
Innovation Solution
A method for manufacturing a split gate type semiconductor memory device involves forming an oxide-nitride-oxide layer over a semiconductor substrate, creating a recess, and sequentially depositing and etching spacer oxide and nitride films to ensure uniformity of charge trap nitride films, resulting in self-aligned and symmetrically formed split gates with consistent lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography is used to form photoresist pattern for split gates, then the split gates can be formed with defined geometry, but overlay variation causes non-uniform lengths of nitride films reducing manufacturing precision
Solution Approach 1:
A mandrel structure is formed beforehand with precise dimensions, and spacer films are deposited on its sidewalls to define the split gate regions. This preliminary formation of the mandrel with controlled geometry enables subsequent self-aligned etching processes that produce uniform nitride film lengths without relying on photolithography overlay precision.
Solution Approach 2:
The mandrel structure serves as an intermediary element that mediates the formation of split gates. By using the mandrel's sidewalls as a template for spacer deposition and subsequent self-aligned etching, the process transfers precision from the mandrel fabrication (which can be controlled by CMP and etch uniformity) to the final split gate structure, eliminating photolithography overlay errors.
2Ease of manufacture
If conventional photolithography process is used, then split gates can be formed, but overlay errors cause variations in memory cell characteristics reducing reliability
Solution Approach 1:
The mandrel structure is formed in advance with precisely controlled dimensions through deposition and CMP processes. This preliminary structure serves as a template that ensures uniform spacing and alignment for subsequent split gate formation, eliminating the reliability issues caused by photolithography overlay variations in memory cell characteristics.
Solution Approach 2:
The spacer films automatically conform to the mandrel sidewalls through physical vapor deposition or chemical vapor deposition, creating self-aligned structures. The etching process then uses these spacers as masks to define the split gates, with the entire process being self-aligned and insensitive to photolithography overlay errors, thereby ensuring uniform memory cell characteristics.
3Ease of manufacture
If split gates are formed by etching with photoresist mask, then gate structure can be created, but misalignment generates length differences in nitride films
Solution Approach 1:
The mandrel structure acts as an intermediary that replaces the photoresist mask. By depositing spacer films on the mandrel sidewalls and using them as etch masks, the process achieves self-aligned etching that produces uniform split gate lengths. This eliminates the misalignment problems inherent in photoresist-based masking while maintaining ease of manufacture through standard deposition and etching processes.
Solution Approach 2:
The mandrel is formed beforehand with precisely controlled geometry, and spacer films are deposited on its sidewalls before the etching step. This preliminary preparation ensures that the etching process has a self-aligned mask that guarantees uniform split gate lengths, eliminating the need for photolithography alignment while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniformity in memory cell characteristics, enhancing the reliability of semiconductor devices by eliminating variations caused by photolithography overlay errors.
Implementation Method 1
sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern
Implementation Method 2
sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern
Implementation Method 3
forming a recess over the semiconductor substrate by etching the ONO layer
Data Source
AI summary
Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.