Split-Gate Memory Arrays With Vertical Channels
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Solution Overview
Problem
Existing memory technologies face challenges in achieving high bit densities and stability of data states due to short-channel effects, which render memory cells inoperable at scaled feature sizes, leading to excessive leakage and inability to discriminate memory states.
Innovation Solution
The implementation of a memory array with split-gate memory cells featuring a vertical channel configuration and dual dielectric stacks to store charge, allowing for channel length flexibility and reduced short-channel effects, thereby increasing bit density and stabilizing the lowest data state with a smaller threshold-voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled to sub-10 nanometer dimensions to increase bit density, then storage capacity improves, but short-channel effects cause excessive leakage and render cells inoperable
Solution Approach 1:
The patent transitions from planar memory cell architecture to a vertical channel configuration where the channel extends in the vertical dimension rather than laterally. This dimensional change allows the channel length to be decoupled from the lateral feature size, enabling sub-10 nanometer scaling while maintaining sufficient channel length to suppress short-channel effects and prevent excessive leakage.
Solution Approach 2:
The patent divides the gate structure into multiple segments along the vertical channel, creating a multi-level gate architecture. This segmentation allows independent control of different channel regions and enables the channel to be sufficiently long for suppressing short-channel effects while fitting within a compact vertical space, thus resolving the contradiction between high bit density and reliable operation.
2Reliability
If channel length is increased to reduce short-channel effects and leakage, then device reliability improves, but memory cell area increases reducing bit density
Solution Approach 1:
The patent resolves this contradiction by extending the channel in the vertical dimension rather than laterally. The vertical channel configuration allows the channel length to be increased for reducing leakage while the memory cell footprint in the lateral plane remains small, thus achieving both improved reliability and high bit density simultaneously.
3Ease of manufacture
If conventional gate dielectric structures are used in scaled memory cells, then manufacturing simplicity is maintained, but inability to discriminate memory states occurs due to short-channel effects
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple dielectric layers with different properties (e.g., tunnel dielectric, blocking dielectric, and charge trap layers). This composite structure provides the necessary electrical characteristics for forming distinct memory states and discriminating between them, while being integrated into the vertical channel architecture to maintain manufacturability through established thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased bit density and stability of data states by avoiding short-channel effects, reducing device leakage, and minimizing under/over erasures, resulting in improved memory performance at sub-10 nanometer dimensions.
Implementation Method 1
a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor
Data Source
AI summary
In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.