Split Gate Memory Yield via Dummy Cell Etching
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Solution Overview
Problem
The manufacturing process of semiconductor devices with MONOS type nonvolatile memory cells of a split gate structure faces challenges in improving production yield due to unwanted processing effects on existing memory cells during the formation of peripheral circuit gate electrodes, leading to defects and reduced reliability.
Innovation Solution
A method involving the sequential formation of gate insulation films, conductive films, and anisotropic etching to create selective and memory gate electrodes, ensuring precise alignment and minimizing interference with existing memory cells, thereby improving the production yield of semiconductor devices with split gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography and dry etching are used to form gate electrodes in peripheral circuit regions after MONOS type nonvolatile memory cells are formed, then field-effect transistors can be manufactured with standard processes, but unnecessary processing is applied to memory cells causing defects and reduced production yield
Solution Approach 1:
The substrate is divided into distinct processing zones: a first region for MONOS type nonvolatile memory cells and a second region for field-effect transistors. Different gate electrode formation processes are applied to each region, allowing standard photolithography/dry etching in the second region while protecting the first region from unnecessary processing that would cause defects
Solution Approach 2:
Different process conditions and structures are applied to different regions: the first region uses a first gate insulation film with specific properties suitable for MONOS cells, while the second region uses a second gate insulation film with properties suitable for standard FETs. This localized optimization allows each region to receive appropriate processing without adversely affecting the other
2Adaptability or versatility
If gate electrodes are formed using photolithography and dry etching after memory cells are formed, then peripheral circuits can be integrated, but processing interference causes defects in existing memory cells
Solution Approach 1:
The manufacturing process is segmented into region-specific steps: gate insulation film formation, conductive film deposition, and etching are performed differently in the first region (memory cells) versus the second region (peripheral circuits). This allows high-precision formation of both MONOS cells and FETs without cross-contamination of processing effects
Solution Approach 2:
Gate insulation films and conductive films are formed with predetermined patterns and properties before final etching steps. The first gate insulation film is formed with thickness and material properties optimized for MONOS cells, while the second gate insulation film is optimized for FETs, ensuring each region achieves its required precision before subsequent processing
Data Source
AI summary
The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.