Split-Gate Trench MOSFET Gate Formation Without Wafer Bowing

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Solution Overview

Problem

The fabrication of split-gate trench MOSFETs is hindered by thermal bowing of Si wafers due to thermally grown silicon dioxide layers, which becomes more severe in high-voltage MOSFETs with deep trenches and thick oxide liners.

Innovation Solution

A method involving the formation of trenches on either side of a source polysilicon rib with inner walls formed by a deposited insulator, using a mask material and photoresist to selectively etch the insulator, and depositing gate polysilicon bars with a thermally grown insulator between the gate and epitaxial layers, reducing the risk of thermal bowing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thermally grown silicon dioxide layer is used as inter poly oxide, then good electrical insulation is achieved, but thermal bowing of Si wafers occurs which worsens with deep trenches and thick oxide liners

Engineering Contradiction:
Improveelectrical insulationVSAvoidwafer flatness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the formation method of the inter poly oxide from thermal growth to deposition. Specifically, it uses chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the insulator layer, which eliminates the thermal stress that causes wafer bowing while maintaining the required electrical insulation properties. This parameter change in the manufacturing process resolves the contradiction between achieving good insulation and maintaining wafer flatness.

Inventive Principle:
Principle #35Parameter changes

2Strength

If deep trenches and thick oxide liners are utilised in high voltage MOSFETs, then breakdown voltage is improved, but thermal bowing becomes more severe

Engineering Contradiction:
Improvebreakdown voltageVSAvoidwafer flatness
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent replaces the thermal field (heat-based thermal oxidation) with a chemical field (CVD or ALD deposition) to form the inter poly oxide layer. This substitution eliminates the thermal stress mechanism that causes wafer bowing, allowing deep trenches and thick oxide liners to be used for high breakdown voltage without the accompanying severe thermal bowing problem.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents significant thermal bowing in split-gate trench MOSFETs, allowing for the creation of devices with improved reliability and performance, especially in high-voltage applications.

Implementation Method 1

with inner walls of the trenches being formed by a deposited insulator

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

providing an insulator on the epitaxial layer... an insulator between the gate polysilicon and the epitaxial layer may be thermally grown

Methodology Applied
Scientific EffectThermal Oxidation: Oxidation

Data Source

PatentUS20240178289A1Mosfet gate formation
Publication Date: 2024.05.30 NEXPERIA BV
  • US20240178289A1 patent drawing
  • US20240178289A1 patent drawing
  • US20240178289A1 patent drawing

AI summary

A method of forming a gate of a split-gate trench MOSFET in an epitaxial layer is provided, the epitaxial layer includes a source polysilicon rib which extends perpendicularly to a plane of the layer; providing trenches on either side of an upper portion of the source polysilicon rib, with inner walls of the trenches formed by a deposited insulator, providing mask material which extends into the trench, providing photoresist on the epitaxial layer and using photolithography to pattern the photoresist, using the photoresist to etch the insulator, a portion of the insulator in contact with the source polysilicon is protected from etching by the mask, removing the mask and forming trenches on either side of the source polysilicon, each trench having an inner wall formed by the insulator which was protected from etching providing an insulator on the epitaxial layer, and providing a bar of gate polysilicon in each trench.