Split-Gate Trench MOSFET Structure for Lower Gate-Source Capacitance

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Solution Overview

Problem

The split gate trench power MOSFET structure faces challenges with high capacitance between the gate electrode and the source electrode, and the manufacturing process is complex due to variations in insulating layer thickness.

Innovation Solution

A trench metal-oxide semiconductor field-effect transistor (MOSFET) manufacturing method that involves forming a gate trench in a substrate, creating a sidewall insulating layer, and forming source and upper electrodes with specific configurations to reduce capacitance and simplify the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a split gate trench power MOSFET structure is used to achieve high breakdown voltage and low drain-source resistance, then the power MOSFET performance is improved, but the capacitance between gate electrode and source electrode increases

Engineering Contradiction:
Improvebreakdown voltage and drain-source resistanceVSAvoidcapacitance between gate and source
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The gate electrode is divided into two separate gates (first gate and second gate) positioned at different depths within the gate trench. This segmentation allows each gate to control different channel regions independently, reducing the overlapping area between the gate electrode and source electrode, thereby reducing parasitic capacitance while maintaining high breakdown voltage and low drain-source resistance through optimized electric field distribution.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If a split gate trench power MOSFET structure is used to reduce power loss, then the efficiency is improved, but the manufacturing process becomes more difficult due to insulating layer thickness variations

Engineering Contradiction:
Improvepower lossVSAvoidmanufacturing process difficulty
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

A thick insulating layer is formed at the bottom of the gate trench before depositing the conductive layers for the first and second gates. This preliminary insulating layer serves as a baseline that compensates for subsequent thickness variations in the gate insulating layer, ensuring uniform total insulating thickness beneath both gates. This approach simplifies manufacturing by eliminating the need for precise thickness control during subsequent deposition steps, while still achieving the desired low power loss through reduced parasitic capacitance.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed method effectively reduces the capacitance between the gate and source electrodes, simplifies the manufacturing process, and enhances the efficiency of power semiconductor devices.

Implementation Method 1

forming a sidewall insulating layer within the gate trench

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Implementation Method 2

forming a source electrode in a lower region of the gate trench by depositing a first conductive layer on the sidewall insulating layer

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS12317546B2Split gate power MOSFET and split gate power MOSFET manufacturing method
Publication Date: 2025.05.27 SK KEYFOUNDRY INC
  • US12317546B2 patent drawing
  • US12317546B2 patent drawing
  • US12317546B2 patent drawing

AI summary

A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.