Split-Gate Trench MOSFET Structure for Smaller Cell Pitch

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Solution Overview

Problem

Trench MOSFET scaling is limited by the area consumed by shielding layers, which restricts total pitch scalability as higher-power applications demand smaller cell pitches.

Innovation Solution

A split-gate MOSFET structure is implemented with a high-k dielectric layer in the lower portion of the trench and a low-k dielectric layer in the upper portion, eliminating the need for a gate shielding layer and reducing the electrical field at the trench bottom without increasing gate capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a shielding layer is implanted to block high electrical field from reaching the gate oxide, then the gate oxide is protected from electrical field damage, but the cell pitch increases due to the area consumed by the shielding layer

Engineering Contradiction:
Improvegate oxide protectionVSAvoidcell pitch
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The gate structure is divided into two distinct parts: a bottom gate electrode positioned in the lower portion of the trench and a top gate electrode positioned in the upper portion of the trench. This segmentation allows the bottom gate electrode to provide shielding protection to the gate oxide while the top gate electrode maintains the necessary electrical field for device operation, thereby protecting the gate oxide without requiring additional shielding layer area that would increase cell pitch

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shielding function is transitioned from a lateral shielding layer approach to a vertical positioning approach. By placing the bottom gate electrode in the lower portion of the trench and the top gate electrode in the upper portion, the shielding function is achieved through vertical spatial arrangement rather than lateral expansion, thus reducing cell pitch while maintaining protection

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the cell pitch is reduced to improve scalability, then device density increases, but the shielding layer area becomes a limiting factor that prevents further pitch reduction

Engineering Contradiction:
Improvedevice densityVSAvoidshielding layer area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The shielding function and the gate control function are merged into a single integrated split-gate structure. The bottom gate electrode provides both shielding protection and partial gate control, while the top gate electrode provides the remaining gate control. This merging eliminates the need for a separate shielding layer, allowing cell pitch reduction and improved device density

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bottom gate electrode serves multiple functions: it provides shielding protection to the gate oxide, contributes to gate control functionality, and enables device operation. This multi-functionality eliminates the need for dedicated shielding layer area, allowing further pitch reduction and improved scalability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances scalability by reducing the electrical field at the trench bottom, allowing for smaller pitches without the need for a shielding layer, thus improving device performance.

Implementation Method 1

forming a high-k dielectric layer within a trench of a transistor... forming a bottom electrode over the high-k dielectric layer... reducing the electrical field at the trench bottom

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20260026071A1Split-gate structure of transistor
Publication Date: 2026.01.22 APPLIED MATERIALS INC
  • US20260026071A1 patent drawing
  • US20260026071A1 patent drawing
  • US20260026071A1 patent drawing

AI summary

Disclosed herein are devices and methods for forming split-gate transistors. In some embodiments, a method may include forming a high-k dielectric layer within a trench of a transistor, and forming a bottom electrode within a lower portion of the trench, wherein the bottom electrode is formed over the high-k dielectric layer. The method may further include forming a low-k dielectric layer over the bottom electrode, and forming a gate material over the low-k dielectric layer.