Split-Gate Trench MOSFET Etching for Contact CD and RDSON
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Solution Overview
Problem
Prior semiconductor devices face limitations in minimum contact CD and misalignment control, as well as silicon etch aspect ratio, which restrict the performance of split gate trench MOSFETs in achieving low RDSON capabilities at respective reverse breakdown voltages.
Innovation Solution
A method for manufacturing a trench-gate semiconductor device involving a two-step trench etching process, where the second trench is wider and deeper than the first trench, with a nitride spacer and oxide layer used to control etching, and a sacrificial oxide layer to reduce defects, resulting in improved reverse breakdown voltage and On-state resistance capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional single-step trench etching process is used, then the manufacturing process is simpler and faster, but the minimum contact CD control and misalignment precision are insufficient
Solution Approach 1:
The single-step trench etching process is divided into two sequential etching steps: a first etching step that creates an initial trench structure, and a second etching step that refines the trench dimensions. This segmentation allows for better control of the minimum contact CD and reduced misalignment by enabling intermediate inspection and adjustment between steps.
Solution Approach 2:
The first etching step performs preliminary trench formation with relaxed precision requirements, creating a foundation structure. Subsequent steps then refine the dimensions with higher precision, allowing the final trench dimensions to achieve the required minimum contact CD control without requiring extreme precision in every step.
2Productivity
If a conventional single-step trench etching process is used, then the manufacturing process is faster, but the etch aspect ratio control is insufficient
Solution Approach 1:
The etching process is segmented into multiple steps with different etch conditions optimized for specific aspects: the first step handles the initial deep etching with conditions optimized for vertical penetration, while the second step refines the trench walls with conditions optimized for aspect ratio control and dimensional precision.
Solution Approach 2:
Different etching parameters (such as etch rate, plasma power, gas flow rates, and temperature) are changed between the first and second etching steps. The first step uses parameters optimized for speed and depth, while the second step uses parameters optimized for precision and aspect ratio control, thereby achieving both high productivity and precise etch aspect ratio control.
3Reliability
If trench structures are made deeper and narrower to improve device performance, then reverse breakdown voltage increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The multi-step etching process segments the challenging task of creating deep, narrow trenches into manageable stages. Each step contributes to the final geometry with controlled precision, accumulating the required depth and narrowness while maintaining dimensional control that would be difficult to achieve in a single step.
Solution Approach 2:
The first trench structure serves as an intermediary element that facilitates the creation of the final deep, narrow trench. The intermediate structure allows for progressive refinement of dimensions, enabling the achievement of high reverse breakdown voltage characteristics with controlled manufacturing precision through multiple refinement stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reverse breakdown voltage and On-state resistance of semiconductor devices by creating a more precise and controlled trench structure, addressing the limitations of existing technologies.
Implementation Method 1
a first trench is etched from a top side of the epitaxial layer towards a bottom side
Implementation Method 2
a sacrificial oxide layer is formed on inner walls of the first trench and/or inner walls of the second trench to reduce etch defects
Data Source
AI summary
A method of manufacturing a semiconductor trench-gate semiconductor device is provided, that includes a trench divided into a first trench and a second trench and the source poly is arranged in the second trench and a gate poly is arranged in the first trench and separated from the source poly by means of an inter poly oxide layer. The width of the second trench is larger than the width of the first trench and the depth of the second trench is larger than the depth of the first trench and the liner oxide layer is thicker than the gate oxide layer. Also, the ratio between the first trench width A and the second trench width B is in a range from 1:1.7 to 1:2.