Split-Gate Trench MOSFET Layout for Self-Aligned Source Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power semiconductor devices, particularly split-gate trench MOSFETs, face challenges in achieving reduced cell pitch due to limitations in lithography definition and alignment tolerance, leading to imbalanced threshold voltage and on-resistance, which affects device performance and reliability.
Innovation Solution
The semiconductor power device incorporates split-gate trench regions with insulating spacer regions and plug regions to improve alignment and doping concentration, enabling accurate channel formation and balanced current flow, while the manufacturing method ensures reliable alignment of contact regions and source contacts through etching and doping processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell pitch is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to lithography definition and alignment tolerance limitations
Solution Approach 1:
The source contact is self-aligned to the split-gate trench regions through the formation process sequence, eliminating the need for separate alignment steps. The contact regions are formed between the trench regions, and the source contact automatically aligns to both, ensuring consistent contact-to-trench distance without relying on lithography alignment tolerance
Solution Approach 2:
The contact regions of first conductivity type act as intermediary structures that mediate the alignment between the source contact and the split-gate trench regions. By forming these contact regions in the mesa region between adjacent trenches, they serve as reference points that define the source contact position, thereby improving manufacturing precision
2Reliability
If contact-to-trench alignment is improved to balance threshold voltage, then reliability is improved, but device complexity increases due to additional alignment constraints
Solution Approach 1:
The gate structure is segmented into two separate trench regions with a mesa region between them. This segmentation allows the source contact to be formed in the mesa region, naturally positioning it equidistant from both trench regions. The segmentation thus simplifies the alignment process while ensuring balanced threshold voltage across the device
Solution Approach 2:
The split-gate structure introduces asymmetry by separating the gate into two distinct regions, which paradoxically simplifies the alignment requirement. Instead of aligning a single contact to a complex multi-trench structure, the asymmetric segmentation allows the contact to be formed in the intervening mesa region, automatically achieving symmetric alignment to both trenches
Data Source
AI summary
A semiconductor power device having an active region, the active region of the device including at least two split-gate trench regions, and the two laterally adjacent split-gate trench regions are separated by a mesa region, and two or more contact regions of a first conductivity type located in the mesa region. The contact regions of a first conductivity type are in contact with the two adjacent split-gate trench regions so that, in use, a channel is formed along a side of each split-gate trench region. The device further includes at least two insulating spacer regions located over and aligned with the two or more contact regions of a first conductivity type, and a source contact extending from an upper surface of the device within the mesa region and between the at least two insulating spacer regions.