Split-Gate Trench MOSFET Structure for Low Capacitance Cell Scaling
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Solution Overview
Problem
Existing power trench MOSFET devices face challenges in achieving stable breakdown voltage and high cell density due to high parasitic capacitance and input capacitance, which affects switching characteristics and power consumption.
Innovation Solution
A semiconductor device with a split gate trench structure, where the shield electrode is formed at the lower portion of the trench and the gate electrode at the upper portion, with optimized thickness ratios and inter-electrode insulating layers to reduce parasitic capacitance and input capacitance, allowing for improved switching characteristics and cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes are formed on both sides of the upper portion of the shield poly electrode in a triple poly structure, then the breakdown voltage can be maintained, but the parasitic capacitance between the gate electrode and source electrode increases
Solution Approach 1:
The patent divides the gate electrode structure into two separate parts: a first gate electrode formed on one side of the shield electrode and a second gate electrode formed on the other side. This segmentation allows each gate electrode to be independently positioned and sized, reducing the overall parasitic capacitance while maintaining the breakdown voltage protection function through the distributed configuration.
Solution Approach 2:
The patent transitions from a planar gate electrode configuration to a three-dimensional split gate structure that extends vertically along the trench. The gate electrodes are positioned at different heights and locations within the trench, utilizing the vertical dimension to reduce capacitive coupling between the gate and source while maintaining electrical field control for breakdown voltage protection.
2Object-generated harmful factors
If the thickness of the insulating layer between the gate poly electrode and shield poly electrode is increased to improve parasitic capacitance, then the capacitance value decreases, but the trench width increases making it difficult to secure small cell pitch
Solution Approach 1:
The patent segments the insulating layer into multiple distinct layers: a first insulating layer between the shield electrode and first gate electrode, and a second insulating layer between the shield electrode and second gate electrode. This segmentation allows optimized thickness distribution that reduces parasitic capacitance while maintaining a compact overall trench width for high cell density.
Solution Approach 2:
The patent optimizes the thickness parameters of the insulating layers and gate electrodes to achieve the desired capacitance reduction without increasing trench width. By carefully controlling the thickness of each insulating layer and the positioning of gate electrodes, the design achieves low parasitic capacitance while maintaining small cell pitch for high productivity.
3Reliability
If two gate poly electrodes are formed on both sides of the top of the shield electrode, then the breakdown voltage is secured, but the input capacitance (Ciss) increases resulting in increased gate charges and switching loss
Solution Approach 1:
The patent segments the gate electrode system into first and second gate electrodes positioned on opposite sides of the shield electrode, with each electrode having optimized dimensions and positioning. This segmentation reduces the total gate-to-source capacitance compared to a conventional single wide gate electrode, thereby reducing the input capacitance and gate charges required for switching while maintaining breakdown voltage protection.
Solution Approach 2:
The shield electrode acts as an intermediary structure that provides electrical field control and breakdown voltage protection while being electrically isolated from the gate electrodes by insulating layers. This intermediary configuration allows the gate electrodes to be positioned closer to the channel region, reducing capacitance and switching loss while the shield electrode maintains the required breakdown characteristics.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; an epitaxial layer disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shield insulating layer formed inside the plurality of trenches; a shield electrode surrounded by the shield insulating layer and disposed inside the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region formed on an upper portion of the epitaxial layer located between the plurality of trenches; a source region formed on the body region; an inter-layer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region.