Split-gate Power MOSFET with Semi-insulating Field Plate
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving high switching speed without premature breakdown, as reducing the gate-to-drain capacitance can lead to high on-resistance and increased electric fields, which can cause device failure.
Innovation Solution
A split gate planar power FET structure incorporating a semi-insulating field plate connected to the source electrode, which suppresses high electric fields and prevents premature breakdown while maintaining high switching speed by minimizing RC delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate-to-drain capacitance is reduced to achieve high switching speed, then the switching speed is improved, but the on-resistance increases and electric fields become concentrated causing premature breakdown
Solution Approach 1:
The gate structure is divided into two separate gates: a first gate positioned over the channel region and a second gate positioned over the drain region. This segmentation allows independent control of the channel and drain regions, enabling the first gate to control channel formation for high switching speed while the second gate manages electric field distribution to prevent premature breakdown.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the first gate and the second gate. This dielectric layer electrically isolates the two gates while allowing them to work together in controlling the device characteristics, enabling the first gate to provide high switching speed and the second gate to prevent premature breakdown without direct electrical interaction.
2Reliability
If a dummy gate is added to reduce electric field at the gate edge, then premature breakdown is prevented, but additional capacitance is produced reducing switching speed
Solution Approach 1:
Instead of using a single dummy gate structure, the invention segments the gate function into two distinct gates positioned at different locations. The first gate over the channel provides switching control, while the second gate over the drain region specifically addresses electric field management, eliminating the need for a dummy gate that would add capacitance.
Solution Approach 2:
The second gate is specifically positioned over the drain region where electric field concentration occurs during shutdown. This localized placement allows the second gate to address the specific problem of premature breakdown at the drain-gate interface without adding unnecessary capacitance to the channel region that would slow down switching.
3Quantity of substance
If the space between adjacent p-type body regions is not reduced to maintain on-resistance, then on-resistance is maintained, but the split gate results in high electric field at the gate edge in the off state
Solution Approach 1:
The harmful electric field concentration at the gate edge is extracted and managed by the second gate positioned over the drain region. This separate gate structure takes out the electric field management function from the first gate, allowing the first gate to maintain proper spacing for on-resistance while the second gate independently manages the electric field at the drain-gate interface.
Solution Approach 2:
The invention changes the electrical parameters by introducing a second gate that can independently control the electric field distribution in the drain region. This parameter change allows the device to maintain the physical spacing between p-type body regions for proper on-resistance while electrically managing the electric field through the second gate's control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semi-insulating field plate effectively reduces the risk of premature breakdown and maintains high switching speed by ensuring no static current during the off-state and minimal transient current during switching, thus enhancing the device's reliability and performance.
Implementation Method 1
a semi-insulating field plate (34), the semi-insulating field plate (34) being on the top of the thin dielectric layer (33) and contacted by the source electrode (22) at the side wall
Implementation Method 2
the split gate (21) and a semi-insulating field plate (34)... minimizing RC delay time
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.