Split-Gate MOSFET Trench Oxide Field Management
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Solution Overview
Problem
Traditional trench MOSFETs face increased cell resistance and higher costs when applying high-voltage above 100 V due to thick trench oxide layers, which also lead to adverse effects like thinner corners and increased cell pitch.
Innovation Solution
A split-gate MOSFET design utilizing two epitaxial layers with different doping concentrations and a trench implantation region at the bottom of each trench, reducing resistance and maintaining the width of the depletion region, while also releasing the maximum electric field at the trench corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick trench oxide layer is used for high-voltage application (100 V or above), then the breakdown voltage is improved, but the cell pitch and cell resistance significantly increase
Solution Approach 1:
The patent applies different oxide layer thicknesses to different regions: a thinner gate oxide layer (50-200 nm) in the cell region and a thicker trench oxide layer (200-500 nm) in the terminal region. This local differentiation allows the device to achieve high breakdown voltage where needed while maintaining compact cell dimensions in the active region, thus resolving the contradiction between breakdown voltage and cell pitch.
Solution Approach 2:
The oxide layer structure is segmented into multiple distinct layers with different functions: gate oxide for channel control, trench oxide for voltage blocking, and field oxide for field management. This segmentation allows each layer to be optimized independently, enabling high breakdown voltage without proportionally increasing overall device dimensions.
2Reliability
If a thick trench oxide layer is used for high-voltage application, then the breakdown voltage is improved, but the manufacturing cost and deposition time increase
Solution Approach 1:
By applying thinner oxide layers only where absolutely necessary (gate oxide in cell region) and using thicker layers only in terminal regions, the total deposition time is significantly reduced compared to uniformly thick oxide layers, while still achieving the required breakdown voltage performance.
Solution Approach 2:
The patent uses sufficient (but not excessive) oxide thickness in each region - thin enough to avoid unnecessary deposition time in the cell region, but thick enough to provide adequate isolation and field control, achieving cost-effective high-voltage performance.
3Reliability
If a thick trench oxide layer is used for high-voltage application, then the breakdown voltage is improved, but the corners of the trench oxide layer become thinner and adverse effects occur
Solution Approach 1:
The patent addresses corner thickness issues by implementing a multi-layer oxide structure where the field oxide layer specifically targets and reinforces the trench corner regions. This local reinforcement ensures uniform electric field distribution at critical corner locations without requiring excessive thickness throughout the entire trench structure.
Solution Approach 2:
The field oxide layer is formed in advance to specifically address potential weak points at trench corners before final device operation. This preliminary reinforcement prevents the formation of thin spots and ensures uniform oxide thickness at critical locations from the outset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The split-gate MOSFET achieves reduced resistance and higher breakdown voltage without increasing the trench oxide layer thickness, enabling efficient operation in high-voltage fields up to 100 V or above.
Implementation Method 1
The gate oxide layer is located between the first and second gates and located between the second gate and the second epitaxial layer. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the surface of the trench and the third gate in the terminal region.
Implementation Method 2
The first epitaxial layer is formed on the substrate and has a first doping concentration. The second epitaxial layer is formed on the first epitaxial layer, wherein the second epitaxial layer has a second doping concentration greater than the first doping concentration. The trench implantation region has a third doping concentration less than the first doping concentration.
Implementation Method 3
via two epitaxial layers having different doping concentrations and the implantation region at the bottom of each trench, the width of the depletion region for high-voltage application can be maintained
Data Source
AI summary
A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region. The third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.