Split Gate Nanocrystal Memory Integration with Metal Gates
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Solution Overview
Problem
The integration of non-volatile memory devices, such as flash EEPROM, into standard CMOS processes is challenging, especially with the transition from silicon dioxide and polysilicon gate conductors to high-k dielectric materials and metal gate electrodes in high-k metal gate (HKMG) stacks, which complicates the incorporation of split gate thin film storage bitcells into metal gate-last technologies.
Innovation Solution
A compact split gate nanocrystal thin film storage non-volatile memory bitcell is integrated with metal gate transistors using a CMOS metal gate-last fabrication sequence, where a non-metal control gate is formed alongside a metal select gate, enabling the coexistence of embedded flash and metal transistors on the same wafer through a 'control gate-first' fabrication method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials and metal gate electrodes are used in HKMG stacks to improve device performance and reduce feature sizes, then transistor performance is improved, but integration complexity with polysilicon nanocrystal thin film storage bitcells increases
Solution Approach 1:
The gate structure is segmented into two distinct parts: a control gate made of polysilicon for the NVM bitcell and a select gate made of metal for the transistor. This segmentation allows each gate to be optimized for its specific function while simplifying the overall integration process by treating them as separate components that can be formed using different materials and processes.
Solution Approach 2:
Different gate regions are assigned different material qualities: the control gate region uses polysilicon to maintain compatibility with existing NVM fabrication processes, while the select gate region uses metal to achieve the performance benefits of HKMG technology. This local differentiation resolves the integration complexity by allowing region-specific optimization.
2Reliability
If metal gate-last technology is used to form metal gate stacks, then transistor performance is enhanced, but incorporation of split gate thin film storage bitcells becomes more difficult
Solution Approach 1:
The control gate is formed first as a preliminary structure before the metal select gate is deposited. This preliminary action establishes the NVM bitcell foundation early in the process, allowing subsequent metal gate formation to proceed without disrupting the already-formed polysilicon control gate structure.
Solution Approach 2:
A dielectric layer serves as an intermediary between the polysilicon control gate and the metal select gate, enabling the combination of different materials and formation sequences. This intermediary layer facilitates the integration by providing a compatible interface that allows both gate types to coexist on the same substrate.
3Adaptability or versatility
If polysilicon control gate structures are formed first, then metal select gates can be integrated, but process sequencing complexity increases
Solution Approach 1:
The fabrication process is designed to be universal, accommodating both polysilicon-based NVM structures and metal-based transistor gates within the same process flow. The process sequencing is optimized to handle multiple gate types through standardized deposition and patterning steps that work for both material systems.
Data Source
AI summary
A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.