Split Gate Nanocrystal Memory Integration with CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of non-volatile memory devices, such as flash EEPROM, into CMOS processes is challenging due to the damage of NVM bitcell gates during gate last processing steps, especially with the reduction of transistor dimensions and the use of high-k metal gate stacks, which requires innovative fabrication methods to coexist with CMOS transistors on the same substrate.
Innovation Solution
The integration of split-gate nanocrystal thin film storage non-volatile memory bitcells with spacer control gates and high-k metal gate transistors using a gate-last process, where the spacer control gates are formed on recessed substrate control gate channel regions to reduce damage and enable the coexistence of embedded flash and high-k metal gate transistors on the same wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stacks are used to form NVM bitcells, then the gate height can be sufficient for NVM functionality, but the gate last processing steps damage the NVM bitcell gates
Solution Approach 1:
The gate structure is segmented into two distinct parts: a first gate electrode (polysilicon) that serves as the control gate for NVM bitcells, and a second gate electrode (metal) that serves as the control gate for CMOS transistors. This segmentation allows each gate type to be optimized independently - the polysilicon gate remains intact during gate last processing while the metal gate is formed later, resolving the contradiction between NVM gate integrity and gate last process compatibility
Solution Approach 2:
A gate dielectric layer is introduced as an intermediary between the substrate and the gate electrodes. This gate dielectric layer enables the formation of both polysilicon and metal gate structures while protecting the underlying NVM bitcell gates during subsequent processing steps, allowing gate last processing to proceed without damaging the NVM gates
2Length of moving object
If the dimensions of transistors are decreased, then device scaling is achieved, but the gate stack height must be reduced which compromises NVM bitcell functionality
Solution Approach 1:
Different gate stack configurations are applied to different regions of the semiconductor device. NVM bitcell regions maintain taller gate stacks with polysilicon control gates optimized for NVM functionality, while CMOS transistor regions use shorter gate stacks with metal control gates optimized for scaled dimensions. This local differentiation allows transistor scaling without compromising NVM bitcell gate functionality
3Reliability
If high-k metal gate stacks are used for CMOS transistors, then device performance is improved, but integration with polysilicon nanocrystal thin film storage bitcells becomes challenging
Solution Approach 1:
The device is segmented into NVM bitcell regions and CMOS transistor regions with distinct gate stack architectures. This segmentation allows high-k metal gate stacks to be implemented in CMOS regions for improved performance while polysilicon nanocrystal thin film storage bitcells maintain their conventional structure in NVM regions, reducing integration complexity by avoiding the need to modify NVM bitcell gates
Solution Approach 2:
The gate dielectric layer serves multiple functions: it acts as the gate insulator for both polysilicon NVM gates and metal CMOS gates, provides a platform for both gate electrode types, and protects underlying structures during processing. This multi-functionality simplifies the integration of high-k metal gate stacks with polysilicon nanocrystal thin film storage bitcells by using a common foundational layer
Data Source
AI summary
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.