Split-Gate Non-Volatile Memory Device Low Programming Current
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in scaling down due to high programming current requirements and difficulty in utilizing on-chip high voltage generation, leading to limitations in further miniaturization and increased manufacturing costs.
Innovation Solution
A non-volatile memory device design featuring a channel region that provides carriers to a second channel region for injecting into the floating gate, utilizing an oxide-nitride-oxide structure and a control gate layer to facilitate low programming voltage and efficient erase operations, allowing for further scaling and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional stacked gate non-volatile memory device is used, then single transistor per cell is achieved, but high programming current is required which makes it difficult to utilize on-chip high voltage generation
Solution Approach 1:
The channel region is divided into two separate regions: a first channel region and a second channel region. The first channel region provides carriers to the second channel region, which then injects them into the floating gate. This segmentation allows the programming function to be distributed across two channels, reducing the current burden on any single channel and enabling on-chip high voltage generation.
Solution Approach 2:
The first channel region acts as an intermediary that supplies carriers to the second channel region. Instead of requiring the second channel region to draw all programming current directly from the source, the first channel region serves as a carrier source, facilitating the programming operation with reduced current requirements.
2Productivity
If device geometry is scaled down to increase circuit density, then more devices can be fabricated on each wafer, but non-volatile memory devices continue to need high voltages to operate
Solution Approach 1:
By segmenting the channel into two regions, the patent enables a scaling-friendly architecture where the programming function is distributed. This allows smaller device geometries to be used while maintaining the ability to program with lower voltages, as each channel region can be optimized for its specific function.
Solution Approach 2:
The patent changes the operational parameters by using two channel regions with different functions. The first channel region operates to provide carriers, while the second channel region operates to inject carriers into the floating gate. This parameter change enables programming at lower voltages, making the device suitable for scaled geometries where on-chip voltage generation is necessary.
3Ease of operation
If conventional split gate non-volatile memory device is used, then electrical programmability and erasability are achieved, but difficulty in further scaling down and low manufacturability yield occur
Solution Approach 1:
The patent segments the channel into two regions, which provides a more scalable architecture compared to the conventional split gate design. This segmentation allows for better control and easier manufacturing as each channel region can be independently optimized and controlled, improving manufacturability yield while maintaining electrical programmability and erasability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low programming voltage requirements, easier implementation of on-chip charge pump circuits, and improved device performance, making it suitable for further scaling and cost-effective manufacturing.
Implementation Method 1
a first channel region and a second channel region within the semiconductor substrate. The first channel region provides carriers to the second channel region for injecting into the floating gate
Implementation Method 2
utilizing an oxide-nitride-oxide structure and a control gate layer to facilitate low programming voltage and efficient erase operations
Implementation Method 3
Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate
Data Source
AI summary
A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.