Split-Gate Non-Volatile Memory with Sharp Floating Gate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory cells with single-transistor stack gate structures face issues with excessive erase operations leading to leakage current, and while double-transistor structures are larger, they still suffer from poor data retention due to thin tunneling dielectric layers causing current leakage.
Innovation Solution
A split-gate non-volatile memory design featuring a floating gate with sharp portions and a corner not covered by the control gate, where the tunneling dielectric layer covers these sharp portions and the corner, enhancing the FN tunneling effect and increasing the dielectric layer thickness to prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a thin tunneling dielectric layer is used to enable quick erase with low power, then erase efficiency is improved, but data retention deteriorates due to current leakage
Solution Approach 1:
The patent applies different dielectric layer thicknesses at different locations: a thin tunneling dielectric layer (5-15nm) at the sharp portions for efficient electron injection during erase operations, and a thick tunneling dielectric layer (20-50nm) at non-sharp portions for preventing leakage current and maintaining data retention. This local differentiation resolves the contradiction between erase efficiency and data retention.
2Reliability
If a double-transistor structure is introduced to solve leakage current from excessive erase, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent segments the gate structure into multiple independent gates (control gate, erasing gate, and word line) that can be independently controlled. This segmentation allows selective erase operations on specific memory cells, preventing excessive erase leakage current without requiring a double-transistor structure, thus maintaining simplicity while improving reliability.
3Reliability
If a double-transistor structure is used to solve leakage current, then reliability is improved, but memory cell area increases
Solution Approach 1:
The patent designs a single-transistor structure where the gate electrode serves multiple functions: it acts as a control gate for programming operations, an erasing gate for erase operations, and a word line for selective addressing. This multi-functionality eliminates the need for separate transistors, maintaining small cell area while achieving reliable leakage current control through the segmented gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves erase efficiency and data retention by facilitating effective electron injection during erase operations and preventing current leakage, while maintaining a smaller memory cell size.
Implementation Method 1
enhancing the FN tunneling effect
Data Source
AI summary
The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.