Split Gate NVM Cell With High-k Metal Gate Stressor
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Solution Overview
Problem
There is a need to enhance both cost-effectiveness and performance for split gate non-volatile memory (NVM) cells integrated with high-k, metal gate (HKMG) logic transistors, as existing methods struggle to achieve optimal performance while keeping costs low.
Innovation Solution
The solution involves forming a split gate NVM cell with a control gate and a select gate over a continuous channel, using a stack of high-k dielectric, metal gate material, and a conductive layer, where the conductive layer is removed from the select gate, allowing a stressor layer to apply different stresses to the source/drain and channel regions, optimizing the stress distribution for improved mobility and charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a stressor layer is applied to enhance mobility in logic transistors, then mobility improves, but excessive stress can degrade NVM cell performance and charge retention
Solution Approach 1:
The patent applies different stress conditions to different regions: the logic region receives stressor layers for enhanced mobility, while the NVM region uses relaxed or differently stressed layers to preserve charge retention. This spatial differentiation of stress characteristics allows each region to operate under optimal conditions without compromising the other.
Solution Approach 2:
The stress management approach segments the device into distinct regions (logic region and NVM region) with independently optimized stress characteristics. The logic transistor channel receives tensile stress for mobility enhancement, while the NVM trap layer region uses compressive or relaxed stress to maintain charge retention, achieving both goals simultaneously through regional segmentation.
2Reliability
If HKMG transistors are used for logic transistors to improve performance, then logic performance improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs a unified high-k dielectric layer that serves dual functions: as the gate dielectric for HKMG logic transistors requiring high performance, and as the NVM trap layer dielectric requiring high charge retention. This multi-functional material selection reduces manufacturing complexity by eliminating the need for separate dielectric layers for different device types.
Solution Approach 2:
The methodology merges the formation of logic transistors and NVM cells into a single integrated fabrication process. Both device types share common process steps including high-k dielectric deposition, metal gate formation, and stressor layer application, thereby reducing overall manufacturing complexity and enabling cost-effective production of high-performance logic with integrated NVM.
3Reliability
If split gate NVM cell structure is implemented to improve charge retention, then charge retention improves, but device area and complexity increase
Solution Approach 1:
The patent combines the NVM trap layer function with the high-k dielectric layer used for logic transistor gates, merging two previously separate structures into one. This integration eliminates redundant layers and reduces the overall device footprint while maintaining the split-gate NVM cell's charge retention capabilities through shared material and process infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in increased mobility and improved charge retention for the NVM cell, with a greater impact on overall performance due to enhanced stress transfer and reduced stress on the logic gate channel, effectively addressing the challenge of achieving high performance at low cost.
Implementation Method 1
a first type of stress is applied to the source/drains which in turn results in a second type of stress, which is opposite the first type of stress, is applied to the channel of the logic transistor
Data Source
AI summary
Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.