Split Gate Semiconductor Device Overhang Suppression
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Solution Overview
Problem
Conventional methods for manufacturing split gate semiconductor memory devices often result in an overhang shape of the gate member, which hinders the formation of a metal compound layer on the control gate, leading to increased resistance and inefficiencies in the manufacturing process.
Innovation Solution
A method involving the formation of a first gate member on a semiconductor substrate, followed by a spacer with a flattened surface, and a second gate member that covers the first gate and spacer, with subsequent etching to remove the insulating film, thereby suppressing the overhang shape and enabling the formation of a metal compound layer on the control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate member is formed following the conventional method with a spacer, then the control gate is formed in a self-aligned manner with the floating gate, but an overhang shape is generated on the gate member surface
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP layer) on the spacer before forming the gate member. This pre-flattening of the spacer surface prevents the overhang shape from occurring in the first place, while still maintaining the self-aligned formation of the control gate with the floating gate through the spacer structure.
2Productivity
If the insulating film is etched together with the gate member, then the etch-back processing is completed, but the insulating film remains in a protruding shape
Solution Approach 1:
The patent applies local quality by making the planarization layer selectively removable. The planarization layer is formed with different etch selectivity compared to the insulating film, allowing the insulating film to be removed in a protruding shape during etch-back processing while the planarization layer remains to maintain surface flatness and prevent overhang formation.
3Reliability
If the control gate has a protruding structure, then the etch-back is completed, but the resistance of the control gate cannot be reduced
Solution Approach 1:
The planarization layer is formed in advance to create a flat surface, ensuring that when the metal compound layer is subsequently deposited on the control gate, it forms a uniform and complete coverage. This preliminary planarization prevents protruding structures that would otherwise cause incomplete metal compound layer formation and maintain high electrical resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the overhang shape and protruding structure issues, allowing for the formation of a uniform metal compound layer on the control gate, reducing resistance and improving the manufacturing efficiency.
Implementation Method 1
forming a spacer on the first gate member
Implementation Method 2
flattening a surface of the spacer
Implementation Method 3
partially etching the first gate member using the spacer as a mask
Implementation Method 4
forming a second gate member so as to cover the first gate and the spacer having the flattened surface
Implementation Method 5
removing the first insulating film by etching
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.