Split-Gate Power Trench Layout for Leakage-Free Oxide Growth
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Solution Overview
Problem
Conventional methods for manufacturing split gate power devices result in excessive linewidth of the gate trench region, affecting threshold voltage consistency and reducing the quantity of unit cells, while high-density plasma precipitation causes charge leakage and cavities in the silicon oxide layer.
Innovation Solution
The method involves depositing epitaxial layers on a silicon substrate, defining trenches, preparing a voltage support layer, growing inter-polysilicon-layered silicon oxide, and performing ion implantation to form body and source regions, with a passivation layer including silicon nitride or silicon dioxide, and using a lithography process to control critical dimensions and avoid plasma-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density plasma precipitation is used to form silicon oxide between polysilicon layers, then the silicon oxide layer is formed, but plasma bombardment causes charge leakage and cavities in the silicon oxide
Solution Approach 1:
The patent changes the formation method of silicon oxide from high-density plasma precipitation to thermal oxidation. This parameter change in the manufacturing process eliminates plasma bombardment while still achieving complete coverage of silicon oxide between polysilicon layers, thereby preventing charge leakage and cavity formation.
2Reliability
If oxidation process is performed on voltage support dielectric layer at bottom of trenches, then voltage support is provided, but upper parts of trenches are also oxidized causing wide linewidth of gate region
Solution Approach 1:
The patent segments the oxidation process into two distinct stages: first oxidizing the voltage support dielectric layer at the trench bottom, then selectively oxidizing the polysilicon layers. This segmentation prevents unwanted oxidation of the gate region while ensuring proper voltage support, thereby maintaining both threshold voltage consistency and gate linewidth precision.
Solution Approach 2:
The patent performs preliminary oxidation of the voltage support dielectric layer before forming the polysilicon layers. This preliminary action ensures that the voltage support is established first, preventing subsequent oxidation issues when polysilicon is formed, thus maintaining precise gate linewidth control.
3Productivity
If conventional manufacturing method is used, then split gate power device is manufactured, but extent of quantity of unit cells is reduced
Solution Approach 1:
The patent changes the oxidation methodology from conventional high-density plasma precipitation to thermal oxidation. This parameter change eliminates cavity formation and improves the quality of silicon oxide layers, thereby increasing the extent of quantity of unit cells that can be manufactured with the same trench definition accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents excessive linewidth, improves unit cell density and threshold voltage consistency, reduces on-resistance, and eliminates charge leakage and cavities, enhancing device efficiency and manufacturing cost control.
Implementation Method 1
depositing, by performing chemical vapor deposition, one or more epitaxial layers on a surface of a silicon substrate
Implementation Method 2
growing an inter-polysilicon-layered silicon oxide
Implementation Method 3
performing ion implantation to form a body region and a source region
Data Source
AI summary
A split gate power device and a method of manufacturing the same are provided. The method includes: preparing an epitaxial layer; defining trenches; preparing a voltage support layer at a bottom of each of the trenches; preparing a source polysilicon; growing silicon oxide between polysilicon layers; preparing a gate polysilicon; performing ion implantation to form a body region and a source region; preparing contact holes and tungsten plugs; performing etching to form a circuit; and preparing a passivation layer.