Split-Gate Memory Cell Oxide Thinning for Faster Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing method for forming split-gate non-volatile memory cells faces a challenge in achieving optimal erase efficiency due to the thickness constraints of the oxide layer, which must be compatible for both logic devices and memory cells, leading to limited erase performance and increased manufacturing complexity.
Innovation Solution
A method is introduced where the oxide layer is selectively thinned in specific regions to enhance tunneling efficiency between the floating gate and control gate, while maintaining the necessary thickness for logic devices, by forming a first portion with a specific thickness for the logic region, a second portion for the memory cell region, and a third portion along the tunnel region with a reduced thickness for improved erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform oxide layer thickness is used for both logic devices and memory cells, then the oxide layer can provide sufficient insulation for high voltage logic devices, but the erase efficiency of memory cells is limited due to the relatively thick oxide layer
Solution Approach 1:
The patent applies local quality by creating different oxide layer thicknesses in different regions: a first oxide layer with thickness T1 in the logic device region providing thick insulation for high voltage operation, and a second oxide layer with thickness T2 (where T2 < T1) in the memory cell tunnel region enabling efficient electron tunneling. This resolves the contradiction by allowing each region to have the oxide thickness optimal for its specific function.
2Productivity
If the oxide layer is thinned to improve memory cell erase efficiency, then tunneling performance improves, but the insulation capability for high voltage logic devices is compromised
Solution Approach 1:
The patent segments the oxide layer into two distinct portions: a first oxide layer formed in the logic device region with greater thickness for insulation, and a second oxide layer formed in the memory cell tunnel region with reduced thickness for efficient electron tunneling. This segmentation allows the system to simultaneously achieve both thick oxide insulation for logic devices and thin oxide tunneling for memory cells, resolving the contradiction between insulation capability and erase efficiency.
3Manufacturing precision
If separate oxide layer formation processes are used for logic devices and memory cells, then optimal thickness can be achieved for each, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a common oxide layer across the entire substrate first, then selectively removing oxide material in the memory cell regions through patterned etching processes. This preliminary formation of a uniform oxide layer followed by selective removal is simpler than attempting to form different thickness oxide layers simultaneously in different regions, as it uses standard semiconductor fabrication techniques in sequence rather than requiring complex simultaneous patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances erase efficiency and performance of the memory cells without compromising the functionality of the control gates or logic devices, simplifying manufacturing and reducing costs by allowing for a more precise control of oxide layer thickness.
Implementation Method 1
electrons tunnel through this dielectric material during an erase operation
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.