Split Gate Programmable Cell Fabrication via Angle Doping
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Solution Overview
Problem
Existing programmable cells, such as one-time programmable cells, face challenges in efficiently forming a split gate architecture that allows for both select and programming operations with precise control over gate dielectric portions, which affects the formation of resistive paths and storage states in transistors.
Innovation Solution
The method involves angle doping a substrate to selectively dope and etch gate dielectric layers, creating a split gate structure with a thin and thick dielectric portion, allowing for the formation of a resistive path during programming and controlling the channel beneath the gate, using standard CMOS process steps and high K gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a split gate architecture is used with both thick and thin dielectric portions, then programming operation and select operation can be differentiated, but the fabrication process becomes more complex
Solution Approach 1:
The gate dielectric layer is segmented into two distinct portions: a thick dielectric portion for select operation and a thin dielectric portion for programming operation. This segmentation allows differentiated functionality within a single gate structure, enabling both select and programming operations to be performed through the same gate conductor with different voltage applications.
Solution Approach 2:
Different regions of the gate dielectric layer are given different local qualities - the thick dielectric portion has higher breakdown voltage characteristics for select operation, while the thin dielectric portion has lower breakdown voltage characteristics for programming operation. This local differentiation enables the gate structure to perform multiple functions with a unified design.
2Manufacturing precision
If angle doping is used to create selective etch rates, then precise control over dielectric thickness is achieved, but the manufacturing process steps increase
Solution Approach 1:
The gate dielectric layer is preliminarily doped at an angle before the split gate structure is fully formed. This preliminary doping action creates different etch rates in different regions of the dielectric layer, which will be utilized in subsequent etching steps to precisely control the final thickness distribution of the gate dielectric portions.
Solution Approach 2:
Dopant atoms serve as an intermediary mechanism to control the etching process. By introducing dopants at specific angles and concentrations, the etch rate of the gate dielectric layer is modulated in different regions, enabling precise thickness control without requiring complex direct thickness control methods during deposition.
3Reliability
If the thin oxide portion breaks down to form a resistive path, then programming state is achieved, but the risk of unintended breakdown increases
Solution Approach 1:
The breakdown voltage parameter of the gate dielectric is precisely controlled by varying the thickness of the thin dielectric portion. By optimizing this thickness parameter, the breakdown voltage is set to a level that is sufficiently low to enable reliable programming operation but sufficiently high to prevent unintended breakdown during normal select operations, thus achieving a reliable operating window.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of programmable cells with precise control over storage states, allowing for effective one-time programmable memory applications with improved current flow and storage capabilities.
Implementation Method 1
When a programming voltage is applied to the gate conductor, the thin oxide portion breaks down and a resistive path from the channel of the transistor to the gate conductor is formed
Data Source
AI summary
A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.