Split-Gate Memory Read Compensation for Temperature-Shifted Currents
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Solution Overview
Problem
The read current of split gate non-volatile memory cells is adversely affected by changes in operating temperature, which is problematic for applications requiring accurate analog signal storage.
Innovation Solution
The use of supercells, each comprising a pair of memory cells, and differential sense amplifiers to compensate for temperature-induced read current errors by assigning upper and lower program states that offset temperature-induced read current variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory cells are programmed to specific analog values for accurate signal storage, then manufacturing precision is improved, but temperature-induced read current variations cause measurement precision to deteriorate
Solution Approach 1:
The patent applies parameter changes by adjusting read voltages based on temperature conditions. The system modifies read voltage parameters to compensate for temperature-induced read current variations, thereby maintaining measurement precision across different operating temperatures while preserving the accuracy of programmed analog values
Solution Approach 2:
The patent implements feedback through temperature sensing and compensation mechanisms. The system monitors temperature conditions and uses this feedback information to adjust read operations, correcting for temperature-induced errors in real-time to maintain both manufacturing and measurement precision
2Measurement precision
If temperature compensation mechanisms are implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing temperature sensing elements and compensation circuitry that act as mediators between the memory cells and the read operation. These intermediaries measure temperature and provide compensation signals that correct read current variations without requiring fundamental changes to the memory cell structure
Solution Approach 2:
The system changes operational parameters (read voltages) based on temperature conditions rather than changing the physical structure of the memory cells. This parameter-based compensation approach improves measurement precision while minimizing the increase in device complexity compared to structural modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces temperature-induced read current errors by ensuring consistent read current values across varying temperatures, maintaining accuracy in memory cell operations.
Implementation Method 1
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation (e.g., a tunnel oxide) 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling.
Implementation Method 2
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20.
Data Source
AI summary
A method of operating memory cells includes programming memory cells at a first temperature to different program states associated with first read current values confirmed by using nominal read conditions. Modified read conditions are determined such that a second read current for the one memory cells at a second temperature is approximately equal to the first read current value for the one memory cell. A read operation is performed on the memory cells at the second temperature using the modified read conditions to determine respective third read current values. Error read current values are determined as respective differences between the first and third read current values. Upper and lower program states are assigned to respective desired program states, with read currents that correspond approximately to respective determined error read current values, and are separated approximately by a respective target read current value associated with the respective desired program state.